標題: | Bi-mode breakdown test methodology of ultrathin oxide |
作者: | Su, HD Chiou, BS Ko, CY Wu, SY Chang, MH Lee, KH Chen, YS Chao, CP See, YC Sun, JYC 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | ramped voltage;ultrathin oxide;oxide breakdown;reliability;bi-mode |
公開日期: | 1-十二月-2003 |
摘要: | The breakdown detections of ultrathin oxide (1.4-2 nm) using a fast voltage ramp have been studied. It was found that the breakdown voltage test of deep sub-micron technology requires the reduction of the gate area of test patterns and therefore the increase of the number of structures due to a large inversion gate current at a low electrical field (> 0. 1 A/cm(2) at 1 V) caused by the scaling down of oxide thickness. The gate current in accumulation mode is smaller than that in inversion mode by more than two orders of magnitude at a low applied voltage (1 V). The bi-mode model proposed in this paper applies a voltage stress in the inversion mode and detects failure in the accumulation mode to enhance the robustness of the breakdown test and reduce the possibility of pseudo breakdown failure. With the proposed method, a shorter test time with an increased test pattern area to improve the efficiency of the breakdown test of ultrathin oxide is achieved. |
URI: | http://hdl.handle.net/11536/27374 |
ISSN: | 0021-4922 |
期刊: | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS |
Volume: | 42 |
Issue: | 12 |
起始頁: | 7232 |
結束頁: | 7237 |
顯示於類別: | 期刊論文 |