A floating well method for exact capacitance-voltage measurement of nano technology

標題:	A floating well method for exact capacitance-voltage measurement of nano technology
作者:	Su, HD Chiou, BS Wu, SY Chang, MH Lee, KH Chen, YS Chao, CP See, YC Sun, JYC 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	capacitance-voltage;electrical oxide thickness;floating well;nano technology;ultrathin oxide
公開日期:	1-六月-2003
摘要:	Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.
URI:	http://dx.doi.org/10.1109/TED.2003.813329 http://hdl.handle.net/11536/27845
ISSN:	0018-9383
DOI:	10.1109/TED.2003.813329
期刊:	IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume:	50
Issue:	6
起始頁:	1543
結束頁:	1544
顯示於類別：	期刊論文

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