A floating well method for exact capacitance-voltage measurement of nano technology

doi:10.1109/TED.2003.813329

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Su, HD	en_US
dc.contributor.author	Chiou, BS	en_US
dc.contributor.author	Wu, SY	en_US
dc.contributor.author	Chang, MH	en_US
dc.contributor.author	Lee, KH	en_US
dc.contributor.author	Chen, YS	en_US
dc.contributor.author	Chao, CP	en_US
dc.contributor.author	See, YC	en_US
dc.contributor.author	Sun, JYC	en_US
dc.date.accessioned	2014-12-08T15:40:51Z	-
dc.date.available	2014-12-08T15:40:51Z	-
dc.date.issued	2003-06-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TED.2003.813329	en_US
dc.identifier.uri	http://hdl.handle.net/11536/27845	-
dc.description.abstract	Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.	en_US
dc.language.iso	en_US	en_US
dc.subject	capacitance-voltage	en_US
dc.subject	electrical oxide thickness	en_US
dc.subject	floating well	en_US
dc.subject	nano technology	en_US
dc.subject	ultrathin oxide	en_US
dc.title	A floating well method for exact capacitance-voltage measurement of nano technology	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TED.2003.813329	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	50	en_US
dc.citation.issue	6	en_US
dc.citation.spage	1543	en_US
dc.citation.epage	1544	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000184249700017	-
dc.citation.woscount	0	-
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