標題: Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide
作者: Wu, WH
Tsui, BY
Huang, YP
Hsieh, FC
Chen, MC
Hou, YT
Jin, Y
Tao, HJ
Chen, SC
Liang, MS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: high-k dielectric;MOS capacitor;two-frequency capacitance-voltage (C-V) correction;ultrathin oxide
公開日期: 1-五月-2006
摘要: A new circuit model of -five elements has been proposed for the two-frequency capacitance-voltage (C-V) correction of high-k gate dielectric and ultrathin oxide. This five-element circuit model considered the static and dynamic dielectric losses in a lossy MOS capacitor, the parasitic well/substrate resistance, and the series inductance in the cables and probing system. Each of the circuit elements could be easily extracted from the two-frequency C-V and static current-voltage (I-V) measurements if some criteria are well satisfied. In addition, this model can also be transformed into another two four-element circuit models to simplify the analysis and calculations, depending on the gate ea age current.
URI: http://dx.doi.org/10.1109/LED.2006.873423
http://hdl.handle.net/11536/12306
ISSN: 0741-3106
DOI: 10.1109/LED.2006.873423
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 27
Issue: 5
起始頁: 399
結束頁: 401
顯示於類別:期刊論文


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