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公開日期標題作者
1-六月-20064.9-GHz low-phase-noise transformer-based superharmonic-coupled GaInP/GaAs HBT QVCOMeng, CC; Chang, YW; Tseng, SC; 資訊工程學系; Department of Computer Science
4-八月-20055.4GHz-127 dBc/Hz at 1MHz GaInP/GaAs HBT quadrature VCO using stacked transformersMeng, CC; Chen, CH; Chang, YW; Huang, GW; 電信工程研究所; Institute of Communications Engineering
1-一月-1997Algorithms for an FPGA switch module routing problem with application to global routingThakur, S; Chang, YW; Wong, DF; Muthukrishnan, S; 資訊工程學系; Department of Computer Science
2002Arbitrary convex and concave rectilinear module packing using TCGLin, JM; Chen, HL; Chang, YW; 資訊工程學系; Department of Computer Science
2000An architecture-driven metric for simultaneous placement and global routing for FPGAsChang, YW; Chang, YT; 資訊工程學系; Department of Computer Science
2000B*-trees: A new representation for non-slicing floorplansChang, YC; Chang, YW; Wu, GM; Wu, SW; 資訊工程學系; Department of Computer Science
1-十二月-2004A clustering- and probability-based approach for time-multiplexed FPGA partitioningWu, GM; Chao, MCT; Chang, YW; 交大名義發表; National Chiao Tung University
1-一月-2002Comment on "Generic universal switch blocks"Fan, HB; Wu, YL; Chang, YW; 資訊工程學系; Department of Computer Science
1-八月-2003Corner sequence - A P-admissible floorplan representation with a worst case linear-time packing schemeLin, JM; Chang, YW; Lin, SP; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
2000Crosstalk-constrained performance optimization by using wire sizing and perturbationPan, SR; Chang, YW; 資訊工程學系; Department of Computer Science
1-九月-2000Crosstalk-driven interconnect optimization by simultaneous gate and wire sizingJiang, IHR; Chang, YW; Jou, JY; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
24-四月-2006Effect of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints under accelerated electromigrationLiang, SW; Chang, YW; Chen, C; 材料科學與工程學系; Department of Materials Science and Engineering
1-十月-2001Generic ILP-based approaches for time-multiplexed FPGA partitioningWu, GM; Lin, JM; Chang, YW; 資訊工程學系; Department of Computer Science
1998Graph matching-based algorithms for FPGA segmentation designChang, YW; Lin, JM; Wong, DF; 資訊工程學系; Department of Computer Science
1997A graph-theoretic sufficient condition for FPGA/FPIC switch-module routabilityChang, YW; Wong, DF; Wong, CK; 交大名義發表; 資訊工程學系; National Chiao Tung University; Department of Computer Science
1-四月-2003Inductance modeling for on-chip interconnectsTu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Inductance modeling for on-chip interconnectsTu, SW; Shen, WZ; Chang, YW; Chen, TC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004Layout techniques for on-chip interconnect inductance reductionTu, SW; Jou, JY; Chang, YW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2001Matching-based algorithm for FPGA channel segmentation designChang, YW; Lin, JM; Wong, MDF; 資訊工程學系; Department of Computer Science
1998Maximally routable switch matrices for FPD designWu, GM; Chang, YW; 資訊工程學系; Department of Computer Science
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