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公開日期標題作者
1-四月-2010Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its MechanismLiao, Chia-Chun; Chiang, Tsung-Yu; Lin, Min-Chen; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-四月-2011Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film TransistorsMa, William Cheng-Yu; Chiang, Tsung-Yu; Yeh, Chi-Ruei; Chao, Tien-Sheng; Lei, Tan-Fu; 電機工程學系; Department of Electrical and Computer Engineering
1-十二月-2008Characteristics of HfO(2)/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO(2) Gate Dielectric and O(2) Plasma Surface TreatmentMa, Ming-Wen; Chiang, Tsung-Yu; Wu, Woei-Cherng; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-八月-2010Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon NanocrystalsChiang, Tsung-Yu; Wu, Yi-Hong; Ma, William Cheng-Yu; Kuo, Po-Yi; Wang, Kuan-Ti; Liao, Chia-Chun; Yeh, Chi-Ruei; Yang, Wen-Luh; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-十一月-2011Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film TransistorsLiao, Chia-Chun; Lin, Min-Chen; Chiang, Tsung-Yu; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
23-四月-2012Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-kappa Eu2O3 gate dielectricsYen, Li-Chen; Hu, Chia-Wei; Chiang, Tsung-Yu; Chao, Tien-Sheng; Pan, Tung-Ming; 電子物理學系; Department of Electrophysics
2009Electrical Characteristics of High Performance SPC and MILC p-Channel LTPS-TFT with High-kappa Gate DielectricMa, Ming-Wen; Chiang, Tsung-Yu; Yeh, Chi-Ruei; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-七月-2009High-performance p-channel LTPS-TFT using HfO(2) gate dielectric and nitrogen ion implantationMa, Ming-Wen; Chiang, Tsung-Yu; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-七月-2009High-performance p-channel LTPS-TFT using HfO2 gate dielectric and nitrogen ion implantationMa, Ming-Wen; Chiang, Tsung-Yu; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-十月-2008High-program/erase-speed SONOS with in situ silicon nanocrystalsChiang, Tsung-Yu; Chao, Tien-Sheng; Wu, Yi-Hong; Yang, Wen-Luh; 電子物理學系; Department of Electrophysics
1-六月-2009High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming MethodWang, Kuan-Ti; Chao, Tien-Sheng; Wu, Woei-Cherng; Chiang, Tsung-Yu; Wu, Yi-Hong; Yang, Wen-Luh; Lee, Chien-Hsing; Hsieh, Tsung-Min; Liou, Jhyy-Cheng; Wang, Shen-De; Chen, Tzu-Ping; Chen, Chien-Hung; Lin, Chih-Hung; Chen, Hwi-Huang; 電子物理學系; Department of Electrophysics
2011Impact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization TechniqueLiao, Chia-Chun; Lin, Min-Chen; Chiang, Tsung-Yu; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-十一月-2008Impacts of N-2 and NH3 Plasma Surface Treatments on High-Performance LTPS-TFT With High-kappa Gate DielectricMa, Ming-Wen; Chao, Tien-Sheng; Chiang, Tsung-Yu; Wu, Woei-Cherng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-八月-2013Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILCChen, Yi-Hsuan; Yen, Li-Chen; Chang, Tien-Shun; Chiang, Tsung-Yu; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-九月-2009MILC-TFT With High-kappa Dielectrics for One-Time-Programmable Memory ApplicationChiang, Tsung-Yu; Ma, Ming-Wen; Wu, Yi-Hong; Kuo, Po-Yi; Wang, Kuan-Ti; Liao, Chia-Chun; Yeh, Chi-Ruei; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-六月-2012Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash ArrayWang, Kuan-Ti; Hsueh, Fang-Chang; Lu, Yu-Lun; Chiang, Tsung-Yu; Wu, Yi-Hong; Liao, Chia-Chun; Yen, Li-Chen; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-十一月-2010A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon NanocrystalsChiang, Tsung-Yu; Ma, William Cheng-Yu; Wu, Yi-Hong; Wang, Kuan-Ti; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-十一月-2010A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon NanocrystalsChiang, Tsung-Yu; Ma, William Cheng-Yu; Wu, Yi-Hong; Wang, Kuan-Ti; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-一月-2012Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film TransistorsMa, William Cheng-Yu; Chiang, Tsung-Yu; Lin, Je-Wei; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-十一月-2009Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type Flash MemoryWang, Kuan-Ti; Chao, Tien-Sheng; Chiang, Tsung-Yu; Wu, Woei-Cherng; Kuo, Po-Yi; Wu, Yi-Hong; Lu, Yu-Lun; Liao, Chia-Chun; Yang, Wen-Luh; Lee, Chien-Hsing; Hsieh, Tsung-Min; Liou, Jhyy-Cheng; Wang, Shen-De; Chen, Tzu-Ping; Chen, Chien-Hung; Lin, Chih-Hung; Chen, Hwi-Huang; 電子物理學系; Department of Electrophysics
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