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公開日期標題作者
2015A 28nm 36kb High Speed 6T SRAM with Source Follower PMOS Read and Bit-Line Under-DriveHong, Chi-Hao; Chiu, Yi-Wei; Zhao, Jun-Kai; Jou, Shyh-Jye; Wang, Wen-Tai; Lee, Reed; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-AssistChiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-201440 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-AssistChiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Chu, Yuan-Hua; Jou, Shyh-Jye; Chuang, Ching-Te; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
2012Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAMWang, Shao-Cheng; Lin, Geng-Cing; Lin, Yi-Wei; Tsai, Ming-Chien; Chiu, Yi-Wei; Jou, Shyh-Jye; Chuang, Ching-Te; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008A reconfigurable MAC architecture implemented with mixed-V(t) standard cell libraryWang, Li-Rong; Chiu, Yi-Wei; Hu, Chia-Lin; Tu, Ming-Hsien; Jou, Shyh-Jye; Lee, Chung-Len; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014Subthreshold SRAM Macro Design with Pulse-Controlled Dynamic Voltage Scaling (PC-DVS)Zhao, Jun-Kai; Chiu, Yi-Wei; Jou, Shyh-Jye; Chu, Yuan-Hua; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016A Subthreshold SRAM with Embedded Data-Aware Write-Assist and Adaptive Data-Aware KeeperChiu, Yi-Wei; Hu, Yu-Hao; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014次臨界操作及低功率內嵌式靜態隨機存取記憶體設計與實現邱奕瑋; Chiu, Yi-Wei; 周世傑; Jou, Shyh-Jye; 電子工程學系 電子研究所
顯示 1 到 8 筆資料，總共 8 筆