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公開日期標題作者
六月-20163D resistive RAM cell design for high-density storage class memory-a reviewHudec, Boris; Hsu, Chung-Wei; Wang, I-Ting; Lai, Wei-Li; Chang, Che-Chia; Wang, Taifang; Frohlich, Karol; Ho, Chia-Hua; Lin, Chen-Hsi; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural NetworkChang, Chih-Cheng; Liu, Jen-Chieh; Shen, Yu-Lin; Chou, Teyuh; Chen, Pin-Chun; Wang, I-Ting; Su, Chih-Chun; Wu, Ming-Hong; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Wong, H-S Philip; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2015Crossbar array of selector-less TaOx/TiO2 bilayer RRAMChou, Chun-Tse; Hudec, Boris; Hsu, Chung-Wei; Lai, Wei-Li; Chang, Chih-Cheng; Hou, Tuo-Hung; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Interchangeable Hebbian and Anti-Hebbian STDP Applied to Supervised Learning in Spiking Neural NetworkChang, Che-Chia; Chen, Pin-Chun; Hudec, Boris; Liu, Po-Tsun; Hou, Tuo-Hung; 電子工程學系及電子研究所; 光電工程學系; Department of Electronics Engineering and Institute of Electronics; Department of Photonics
2-六月-2016Interface engineered HfO2-based 3D vertical ReRAMHudec, Boris; Wang, I-Ting; Lai, Wei-Li; Chang, Che-Chia; Jancovic, Peter; Frohlich, Karol; Micusik, Matej; Omastova, Maria; Hou, Tuo-Hung; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
24-十一月-2017Internal current amplification induced by dielectric hole trapping in monolayer MoS2 transistorLiu, Pang-Shiuan; Lin, Ching-Ting; Hudec, Boris; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Memristive devices by ALD: design aspects for high density 3D arrays for memory and neuromorphic applicationsHudec, Boris; Chang, Che-Chia; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2018Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive SynapseChang, Chih-Cheng; Chen, Pin-Chun; Chou, Teyuh; Wang, I-Ting; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Recommended Methods to Study Resistive Switching DevicesLanza, Mario; Wong, H-S Philip; Pop, Eric; Ielmini, Daniele; Strukov, Dimitri; Regan, Brian C.; Larcher, Luca; Villena, Marco A.; Yang, J. Joshua; Goux, Ludovic; Belmonte, Attilio; Yang, Yuchao; Puglisi, Francesco M.; Kang, Jinfeng; Magyari-Kope, Blanka; Yalon, Eilam; Kenyon, Anthony; Buckwell, Mark; Mehonic, Adnan; Shluger, Alexander; Li, Haitong; Hou, Tuo-Hung; Hudec, Boris; Akinwande, Deji; Ge, Ruijing; Ambrogio, Stefano; Roldan, Juan B.; Miranda, Enrique; Sune, Jordi; Pey, Kin Leong; Wu, Xing; Raghavan, Nagarajan; Wu, Ernest; Lu, Wei D.; Navarro, Gabriele; Zhang, Weidong; Wu, Huaqiang; Li, Runwei; Holleitner, Alexander; Wurstbauer, Ursula; Lemme, Max C.; Liu, Ming; Long, Shibing; Liu, Qi; Lv, Hangbing; Padovani, Andrea; Pavan, Paolo; Valov, Ilia; Jing, Xu; Han, Tingting; Zhu, Kaichen; Chen, Shaochuan; Hui, Fei; Shi, Yuanyuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2017Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabricationChen, Hong-Yu; Brivio, Stefano; Chang, Che-Chia; Frascaroli, Jacopo; Hou, Tuo-Hung; Hudec, Boris; Liu, Ming; Lv, Hangbing; Molas, Gabriel; Sohn, Joon; Spiga, Sabina; Teja, V. Mani; Vianello, Elisa; Wong, H. -S. Philip; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2020Semi-Empirical RC Circuit Model for Non-Filamentary Bi-Layer OxRAM DevicesMajumdar, Swatilekha; Chen, Ying; Hudec, Boris; Hou, Tuo-Hung; Suri, Manan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
13-二月-2020SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM DevicesKingra, Sandeep Kaur; Parmar, Vivek; Chang, Che-Chia; Hudec, Boris; Hou, Tuo-Hung; Suri, Manan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Three dimensional integration of ReRAMsHudec, Boris; Chang, Che-Chia; Wang, I-Ting; Frohlich, Karol; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 13 筆資料，總共 13 筆