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公開日期標題作者
1-五月-2015A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-AssistLu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2012A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-AssistLu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A 0.92mm(2) 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e ApplicationYen, Shao-Wei; Hu, Ming-Chih; Chen, Chih-Lung; Chang, Hsie-Chia; Jou, Shyh-Jye; Lee, Chen-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2015A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter SuppressionSu, Ming-Chiuan; Chen, Wei-Zen; Wu, Pei-Si; Chen, Yu-Hsiang; Lee, Chao-Cheng; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
200910Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision LoopLin, Yu-Chun; Shiue, Muh-Tian; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter SuppressionSu, Ming-Chiuan; Chen, Wei-Zen; Wu, Pei-Si; Chen, Yu-Hsian; Lee, Chao-Cheng; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
20142.2mW 5GHz 全數位鎖相迴路用於在類比多音收發器安禾杉; Hossameldin Ali Anwar Ibrahim; 周世傑; Jou, Shyh-Jye; 電子工程學系 電子研究所
2008A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital SynchronizationWei, Ting-Chen; Liu, Wei-Chang; Tseng, Chi-Yao; Long, Syu-Siang; Jou, Shyh-Jye; Shiue, Muh-Tian; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015A 28nm 36kb High Speed 6T SRAM with Source Follower PMOS Read and Bit-Line Under-DriveHong, Chi-Hao; Chiu, Yi-Wei; Zhao, Jun-Kai; Jou, Shyh-Jye; Wang, Wen-Tai; Lee, Reed; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nmPreyss, Nicholas; Senning, Christian; Burg, Andreas; Liu, Wei-Chang; Liu, Chun-Yi; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-AssistChiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2014A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-AssistLien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-201440 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-AssistChiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Chu, Yuan-Hua; Jou, Shyh-Jye; Chuang, Ching-Te; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-一月-2013A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting ControlLiao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-AssistChang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2012A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c ApplicationsYen, Shao-Wei; Hung, Shiang-Yu; Chen, Chih-Lung; Chang, Hsie-Chia; Jou, Shyh-Jye; Lee, Chen-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM SystemsNg, Chee-Kit; Chiu, Kang-Lun; Lin, Yu-Chun; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
201350Gb/s 115mW 全數位適應性決策回授等化器與雜訊抑制濾波器吳智傑; Ng, Chee-Kit; 周世傑; Jou, Shyh-Jye; 電機資訊國際學程
201560 GHz多載波濾波器組系統之相位雜訊消除與取樣頻率偏移追蹤等化器姚宇誠; Yao, Yu-Cheng; 周世傑; 劉志尉; Jou, Shyh-Jye; Liu, Chih-Wei; 電子工程學系 電子研究所
201460 GHz頻帶室內無線數位基頻接收機及具時序錯誤容忍功能電路之設計劉瑋昌; Liu, Wei-Chang; 周世傑; 楊家驤; Jou, Shyh-Jye; Yang, Chia-Hsiang; 電子工程學系 電子研究所
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