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公開日期標題作者
1-四月-2008Effects of length scaling on electromigration in dual-damascene copper interconnectsLin, M. H.; Lin, M. T.; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2007Effects of width scaling and layout variation on dual damascene copper interconnect electromigrationLin, M. H.; Chang, K. P.; Su, K. C.; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006Effects of width scaling, length scaling, and layout variation on electromigrationin in dual damascene copper interconnectsLin, M. H.; Chang, K. P.; Su, K. C.; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Investigation of Electrical Characteristics on 25-nm InGaAs Channel FinFET Using InAlAs Back Barrier and Al2O3 Gate DielectricLin, M. H.; Lin, Y. C.; Lin, Y. S.; Sun, W. J.; Chen, S. H.; Chiu, Y. C.; Cheng, C. H.; Chang, C. Y.; 光電系統研究所; 電子工程學系及電子研究所; Institute of Photonic System; Department of Electronics Engineering and Institute of Electronics
1-二月-2013Metal-Gate/High-kappa/Ge nMOS at Small CET With Higher Mobility Than SiO2/Si at Wide Range Carrier DensitiesLiao, C. C.; Ku, T. C.; Lin, M. H.; Zeng, Lang; Kang, Jinfeng; Liu, Xiaoyan; Chin, Albert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise MeasurementLin, M. H.; Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
27-十月-2018On the Electrical Characteristics of Ferroelectric FinFET Using Hafnium Zirconium Oxide with Optimized Gate StackLin, M. H.; Fan, C. C.; Hsu, H. H.; Liu, C.; Chen, K. M.; Cheng, C. H.; Chang, C. Y.; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
2010The Understanding of Strain-Induced Device Degradation in Advanced MOSFETs with Process-Induced Strain Technology of 65nm Node and BeyondLin, M. H.; Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 8 筆資料，總共 8 筆