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1-一月-2011Design Planning with 3D-Via Optimization in Alternative Stacking Integrated CircuitsLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2008Effective Decap Insertion in Area-Array SoC Floorplan DesignLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2008An effective decap insertion method considering power supply noise during floorplanningLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007On increasing signal integrity with minimal decap insertion in area-array SoC floorplan designLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-DesignLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2013Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designsLu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2007Using power gating techniques in area-array SoC floorplan designYeh, Chi-Yi; Chen, Hung-Ming; Huang, Li-Da; Wei, Wei-Ting; Lu, Chao-Hung; Liu, Chien-Nan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 7 筆資料，總共 7 筆