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公開日期標題作者
1981AN ANALYTICAL MODEL FOR HIGH-LOW-EMITTER (HLE) SOLAR-CELLS IN CONCENTRATED SUNLIGHTSHEN, WZ; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1994A CELL-BASED POWER ESTIMATION IN CMOS COMBINATIONAL CIRCUITSLIN, JY; LIU, TC; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
7-十二月-1989CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTSCHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-七月-1993DESIGN OF PSEUDOEXHAUSTIVE TESTABLE PLA WITH LOW OVERHEADSHEN, WZ; HWANG, GH; HSU, WJ; JAN, YJ; 電控工程研究所; Institute of Electrical and Control Engineering
1-十月-1993EFFICIENT OUTPUT PHASE ASSIGNMENT ALGORITHM FOR PLASHSU, WJ; SHEN, WZ; 電控工程研究所; Institute of Electrical and Control Engineering
1-八月-1990EMOTA - AN EVENT-DRIVEN MOS TIMING SIMULATOR FOR VLSI CIRCUITSSHEN, WZ; JOU, SJ; TAO, YS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-二月-1993EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATORJOU, SJ; CHIOU, SH; TAO, YS; SHEN, WZ; 電控工程研究所; Institute of Electrical and Control Engineering
1995Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mappingSHEN, WZ; HUANG, JD; CHAO, SM; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-1986MOTA - A MOSFET TIMING SIMULATORJOU, SJ; JEN, CW; SHEN, WZ; LEE, CL; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-六月-1990MY-BOX REPRESENTATION FOR FAULTY CMOS CIRCUITSCHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1994ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGNSHEN, WZ; TAO, YH; DUNG, LR; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1980THE OPEN-CIRCUIT VOLTAGE OF BACK-SURFACE-FIELD (BSF) P-N-JUNCTION SOLAR-CELLS IN CONCENTRATED SUNLIGHTWU, CY; SHEN, WZ; 電控工程研究所; 奈米中心; Institute of Electrical and Control Engineering; Nano Facility Center
1-四月-1993RESTRUCTURING AND LOGIC MINIMIZATION FOR TESTABLE PLAHWANG, GH; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-1993SEESIM - A FAST SYNCHRONOUS SEQUENTIAL-CIRCUIT FAULT SIMULATOR WITH SINGLE-EVENT EQUIVALENCEWU, CP; LEE, CL; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-1987SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUITJOU, SJ; SHEN, WZ; JEN, CW; LEE, CL; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-十二月-1991SINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITSCHEN, JE; LEE, CL; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 16 筆資料，總共 16 筆