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公開日期標題作者
1-八月-2005Characterization of polysilicon thin-film transistors with asymmetric source/drain implantationShieh, MS; Lin, YJ; Yu, CM; Lei, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006The CMP process and cleaning solution for planarization of strain-relaxed SiGe virtual substrates in MOSFET applicationsShieh, MS; Chen, PS; Tsai, MJ; Lei, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2006Electrical characteristics and reliability of multi-channel polycrystalline silicon thin-film transistorsShieh, MS; Sang, JY; Chen, CY; Wang, SD; Lei, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
15-六月-2000Improvement of polysilicon oxide integrity using NF3-annealingYang, WL; Shieh, MS; Chen, YM; Chao, TS; Liu, DG; Lei, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2005A novel dynamic threshold voltage MOSFET (DTMOS) using heterostructure channel of Si1-yCy interlayerShieh, MS; Chen, PS; Tsai, MJ; Lei, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2000Retardation in the chemical-mechanical polish of the boron-doped polysilicon and siliconYang, WL; Cheng, CY; Tsai, MS; Liu, DG; Shieh, MS; 交大名義發表; National Chiao Tung University
顯示 1 到 6 筆資料，總共 6 筆