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1-六月-2020Experimental Study of 1/f(1+alpha) Noise in Transient Leakage Current of Metal-Insulator-Metal With Stacked High-k Polycrystalline FilmsLin, Hsin-Jyun; Akiyama, Koji; Hirota, Yoshihiro; Akasaka, Yasushi; Nakamura, Genji; Nagai, Hiroyuki; Morimoto, Tamotsu; Watanabe, Hiroshi; 電機工程學系; Department of Electrical and Computer Engineering
1-三月-2011Integrated Batteryless Electron TimerWatanabe, Hiroshi; Ushijima, Tomomi; Hagiwara, Norio; Okada, Chiomi; Tanabe, Takeshi; 電子工程學系及電子研究所; 友訊交大聯合研發中心; Department of Electronics Engineering and Institute of Electronics; D Link NCTU Joint Res Ctr
1-八月-2017Localized Tunneling Phenomena of Nanometer Scaled High-K Gate-StackLin, Po-Jui Jerry; Lee, Che-An Andy; Yao, Chih-Wei Kira; Lin, Hsin-Jyun Vincent; Watanabe, Hiroshi; 電機工程學系; 電信工程研究所; Department of Electrical and Computer Engineering; Institute of Communications Engineering
1-五月-2018Monte Carlo Simulation of Nanowires Array Biosensor With AC ElectroosmosisLee, Che-An; Teramoto, Akinobu; Watanabe, Hiroshi; 電機工程學系; Department of Electrical and Computer Engineering
1-九月-2019Monte Carlo simulation of random dopant fluctuation in C-V characteristics using image charge model and adequately determined length scaleChih-Wei, Yao; Sano, Nobuyuki; Watanabe, Hiroshi; 電機工程學系; 電信工程研究所; Department of Electrical and Computer Engineering; Institute of Communications Engineering
1-一月-2017Monte-Carlo Simulation of Biomolecules' Fluid-Dynamics in Electrolyte Facing Nanowires BiosensorLee, Che-An; Teramoto, Akinobu; Watanabe, Hiroshi; 電機工程學系; Department of Electrical and Computer Engineering
1-一月-2014Nano-meter Scaled Gate Area High-K Dielectrics with Trap-Assisted Tunneling and Random Telegraph NoiseLin, Po-Jui Jerry; Lee, Zhe-An Andy; Yao, Chih-Wei Kira; Lin, Hsin-Jyun Vincent; Watanabe, Hiroshi; 資訊工程學系; 電信工程研究所; Department of Computer Science; Institute of Communications Engineering
1-四月-2014Numerical Study of Very Small Floating IslandsWatanabe, Hiroshi; Yao, Kira (Chih-Wei); Lin, Jerry (Po-Jui); 交大名義發表; 電機資訊學士班; National Chiao Tung University; Undergraduate Honors Program of Electrical Engineering and Computer Science
1-十二月-2018Physics of Discrete Impurities under the Framework of Device Simulations for Nanostructure DevicesSano, Nobuyuki; Yoshida, Katsuhisa; Yao, Chih-Wei; Watanabe, Hiroshi; 電機工程學系; Department of Electrical and Computer Engineering
2012P型SONOS快閃記憶體元件電荷動態分佈之研究邱勇岳; Chiu, Yung-Yueh; 渡邊浩志; Watanabe, Hiroshi; 電信工程研究所
2011Quantitative Discussion on Electron-hole Universal Tunnel Mass in Ultrathin Dielectric of Oxide and Oxide-NitrideWatanabe, Hiroshi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010Statistical Simulation of Metal-Gate Work-function Fluctuation in High-kappa/Metal-Gate DevicesYu, Chia-Hui; Han, Ming-Hung; Cheng, Hui-Wen; Su, Zhong-Cheng; Li, Yiming; Watanabe, Hiroshi; 電機工程學系; Department of Electrical and Computer Engineering
1-十二月-2018Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxideLin, Po-Jui; Su, Chong-Zih; Yao, Chih-Wei; Watanabe, Hiroshi; 電機工程學系; 電信工程研究所; Department of Electrical and Computer Engineering; Institute of Communications Engineering
1-十一月-2010A Tight Binding Method Study of Optimized Si-SiO(2) SystemWatanabe, Hiroshi; Kawabata, Kenji; Ichikawa, Takashi; 電子工程學系及電子研究所; 友訊交大聯合研發中心; Department of Electronics Engineering and Institute of Electronics; D Link NCTU Joint Res Ctr
1-十一月-2010A Tight Binding Method Study of Optimized Si-SiO2 SystemWatanabe, Hiroshi; Kawabata, Kenji; Ichikawa, Takashi; 電子工程學系及電子研究所; 電子與資訊研究中心; Department of Electronics Engineering and Institute of Electronics; Microelectronics and Information Systems Research Center
1-八月-2010Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local TrapWatanabe, Hiroshi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2010Universal Tunnel Mass and Charge Trapping in [(SiO(2))(1-x)(Si(3)N(4))(x)](1-y)Si(y) FilmWatanabe, Hiroshi; Matsushita, Daisuke; Muraoka, Kouichi; Kato, Koichi; 資訊工程學系; 電子與資訊研究中心; Department of Computer Science; Microelectronics and Information Systems Research Center
1-五月-2010Universal Tunnel Mass and Charge Trapping in [(SiO2)(1-x)(Si3N4)(x)](1-y)Si-y FilmWatanabe, Hiroshi; Matsushita, Daisuke; Muraoka, Kouichi; Kato, Koichi; 電子工程學系及電子研究所; 電子與資訊研究中心; Department of Electronics Engineering and Institute of Electronics; Microelectronics and Information Systems Research Center
2014三維多體陷阱模擬林鑫均; Lin, Sin-Jyun; 渡邊浩志; Watanabe, Hiroshi; 電信工程研究所
2014氧化層電場對NAND快閃記憶體保存度影響之研究陳玄澤; Chen, Hsuan-Tse; 渡邊浩志; Watanabe, Hiroshi; 電信工程研究所
顯示 1 到 20 筆資料，總共 20 筆