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學術出版;;Publications

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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Access type: Open accessSubject: search.filters.subject.Flash memory

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Now showing 1 - 10 of 21
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    用於快閃式記憶元件及電路性能與可靠性模擬的元件模式
    (2000)
    莊紹勳
    ;
    Chung Steve S
    ;
    交通大學電子工程系
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    先進低電壓低功率及高效能快閃式記憶體之研究(I)
    (2001)
    莊紹勳
    ;
    Chung Steve S
    ;
    交通大學電子工程系
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    超薄氧化層高等可靠性物理暨次世代快閃式記憶體之前瞻性研究
    (2001)
    陳明哲
    ;
    CHEN MING-JER
    ;
    國立交通大學電子工程研究所
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    P通道快閃式記憶元件在長時間寫入抹除後由熱載子導致的可靠性問題研究
    (1999)
    莊紹勳
    ;
    Chung Steve S
    ;
    交通大學電子工程系
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    深次微米MOSFET穿隧漏電流、鎖定及靜電放電之研究
    (1999)
    陳明哲
    ;
    CHEN MING-JER
    ;
    交通大學電子工程研究所
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    深次微米MOSFET穿隧漏電流、鎖定及靜電放電之研究(II)
    (2000)
    陳明哲
    ;
    CHEN MING-JER
    ;
    交通大學電子工程研究所
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    High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in NOR-Type Flash Memory
    (2010-09-01)
    Wang, Kuan-Ti
    ;
    Chao, Tien-Sheng
    ;
    Wu, Woei-Cherng
    ;
    Yang, Wen-Luh
    ;
    Lee, Chien-Hsing
    For the first time, a high-performance (tau(PGM) = 200 ns/tau(ERS) = 5 ms) cell with superior reliability characteristics is demonstrated in a NOR-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight V(TH) distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.
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    A Hybrid Approach to NAND-Flash-Based Solid-State Disks
    (2010-10-01)
    Chang, Li-Pin
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Replacing power-hungry disks with NAND-flash-based solid-state disks (SSDs) is a recently emerging trend in flash-memory applications. One important SSD design issue is achieving a good balance between cost, performance, and lifetime. This study introduces a hybrid approach to large SSDs that combines MLC NAND flash and SLC NAND flash. Each of these flash architectures has its own drawbacks and benefits, and this study proposes that the two can complement each other. However, there are technical challenges pertaining to data placement, data migration, and wear leveling in heterogeneous NAND flash. The experimental results of our study show that combining 256 MB SLC flash with 20 GB MLC flash produces a hybrid SSD. This hybrid SSD is 1.8 times faster than a purely MLC-flash-based SSD in terms of average response time and improves energy consumption by 46 percent. The proposed hybrid SSD costs only four percent more than a purely MLC-flash-based SSD. The extra cost of a hybrid SSD is very limited and rewarding.
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    An Adaptive, Low-Cost Wear-Leveling Algorithm for Multichannel Solid-State Disks
    (2013-12-01)
    Chang, Li-Pin
    ;
    Chou, Tung-Yang
    ;
    Huang, Li-Chun
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. As flash memory endures only limited program-erase cycles, solid-state disks employ wear-leveling methods to prevent any portions of flash memory from being retired prematurely. Modern solid-state disks must consider wear evenness at both block and channel levels. This study first presents a block-level wear-leveling method whose design has two new ideas. First, the proposed method reuses the intelligence available in flash-translation layers so it does not require any new data structures. Second, it adaptively tunes the threshold of block-level wear leveling according to the runtime write pattern. This study further introduces a new channel-level wear-leveling strategy, because block-level wear leveling is confined to a channel, but realistic workloads do not evenly write all channels. The proposed method swaps logical blocks among channels for achieving an eventually-even state of channel lifetimes. A series of trace-driven simulations show that our wear-leveling method outperforms existing approaches in terms of wear evenness and overhead reduction.