| 標題: | 微瓦級動態電壓與頻率調整之晶片匯流排設計 The Design of UW DVFS On-Chip Bus |
| 作者: | 蘇朝琴 SU CHAU-CHIN 國立交通大學電機與控制工程學系（所） |
| 公開日期: | 2010 |
| 官方說明文件#: | NSC98-2221-E009-137-MY2 |
| URI: | http://hdl.handle.net/11536/100321 https://www.grb.gov.tw/search/planDetail?id=2012195&docId=329353 |
| Appears in Collections: | Research Plans |
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- 微瓦級動態電壓與頻率調整之晶片匯流排設計 / 蘇朝琴;SU CHAU-CHIN
- 在嵌入式爪哇虛擬機器中設計並實做動態電壓頻率調整技術 / 陳裕生;Yusheng Chen;單智君
- A 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems / Chen, Yuan;Lin, Yu-Wei;Tsao, Yu-Chi;Lee, Chen-Yi
- Low-power and High-performance FFT Processors for OFDM Communication Systems / 陳元;Yuan Chen;李鎮宜;Chen-Yi Lee
- 使用機器學習技術進行動態電壓與頻率調整測試分級 / 張耕瑋;趙家佐;Chang, Keng-Wei;Chao, Chia-Tso
- Parallel Architecture Core (PAC)-the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools / Chang, David Chih-Wei;Lin, Tay-Jyi;Wu, Chung-Ju;Lee, Jenq-Kuen;Chu, Yuan-Hua
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