| 標題: | 後次微米時代新興電子設計自動化技術之研究---子計畫三：角落錯誤之矽除錯(III) Silicon Debug for Hard-Corner Design Errors |
| 作者: | 周景揚 JOU JING-YANG 國立交通大學電子工程學系及電子研究所 |
| 關鍵字: | 除錯;矽除錯;可偵錯度;角落錯誤;錯誤區域辨識;錯誤候選邏輯閘排序;錯誤診斷架構;聚焦離子束;版圖調整;可移動訊號候選排序;Debug;Silicon debug;Diagnosibility;Hard-corner errors;Faulty-region identification;Fault-candidate ranking;Fault diagnosis architecture;Focused-ion-beam;Layout adjustment;moving-signal candidate ranking |
| 公開日期: | 2010 |
| 官方說明文件#: | NSC99-2220-E009-010 |
| URI: | http://hdl.handle.net/11536/100617 https://www.grb.gov.tw/search/planDetail?id=2158798&docId=347423 |
| Appears in Collections: | Research Plans |
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