16奈米矽多重閘極電晶體中隨機摻雜導致之特性擾動及其抑制方法

Abstract

隨著矽製程技術的演進，超大型積體電路元件已進入次45 奈米生產技術，除了傳統製程變異效應，隨機摻雜問題所造成的擾動已嚴重的影響了場效應電晶體的特性與可靠度。在去年的計畫中 (隨機摻雜在次20 奈米矽場效應電晶體特性擾動之研究)，吾人已成功地以實驗與理論分析次20 奈米矽場效應電晶體特性之擾動，研究指出20 奈米電晶體臨界電壓的隨機摻雜擾動將高達40 mV，此模擬結果與台積電的實際量測結果(39 mV)非常吻合，此結果已陸續發表於2007年VLSI會議以及IEEE相關期刊。 延續摩爾定律而獲得高性能矽晶片以及高密度元件之觀點，新材料、新製程與新結構的開發是半導體製造上繼續微縮元件的尺寸最有效的策略方案；其中，20 奈米之後電晶體結構的改變儼然已成為非常前瞻與重要的趨勢，因此研究隨機摻雜問題在多重閘極場效電晶體特性之影響已為重要且急迫之課題之一。延續先前計畫所開發之模擬分析方法，本計劃將以兩年之時間完整研究隨機摻雜在16奈米等級多閘極立體場效應電晶體導致的擾動問題及其抑制方法；第一年計畫將結合實驗與理論研究含平面SOI電晶體、雙閘極電晶體、三閘極SOI電晶體、三閘極塊材電晶體、方塊全閘極電晶體、圓形全閘極電晶體、類圓形全閘極電晶體，…等立體元件隨機摻雜導致的電特性擾動，其中關於閘極長度暨製程線寬變化導致的擾動也將一起分析。同時為了壓抑次20 奈米元件中高達40 mV 以上的臨界電壓擾動，吾人於第二年計畫將針對上述的平面與多閘極立體電晶體，在兼具高性能電特性要求之前提下，找尋壓抑擾動之物理機制並從材料與製程之觀點提出有效壓抑擾動的方法，如：摻雜分布之最佳化、閘極工程與閘極高介電材料的使用，…等等，並與台積電進行實驗驗證與製程最佳化。最後根據所研究之壓抑擾動的物理機制與實驗數據，推演能準確描述隨機摻雜導致電特性擾動的解析公式。

As MOSFETs shrink in size, unlike the electrostatic potential in large metal-oxide-semiconductor field effect transistors (MOSFETs), which is controlled by a cloud of remote charges, the electrostatic potential of small MOSFETs is dominated by only a few nearby charges whose contributions are large enough to be distinct. For our NSC project in 2007 entitled: Random-dopant-induced electrical characteristics fluctuation in sub-20 nm field effect transistors, the characteristic fluctuations induced by random dopants in sub-20 nm planar MOSFETs has been successfully investigated. We have, for the first time, theoretically quantified the random-dopant-induced threshold voltage fluctuation which could be 40 mV for 20 nm-gate planar MOSFETs. The calculation is mainly based upon a statistically sound large-scale 3D atomistic device simulation technique developed in our recent work. The estimated result has experimentally verified with the measurement result, the 39 mV threshold voltage fluctuation in 20 nm-gate planar MOSFETs measured from TSMC’s samples. Both the good agreement between simulation and measurement, and mechanism of fluctuation has completely analyzed. The preliminary result has been presented in 2007 VLSI technology symposium and sent for publication in IEEE journals. New material, new processes, and new device structures are the most important issues to continue Moore’s Law in IC industry. For increasing transistor density and enhancing chip performance, the International Roadmap for Semiconductors has forecasted a transition from conventional planar CMOS devices to multiple-gate FETs as high-performance device. Thus, investigation of the random dopant effect in sub-20 nm multiple-gate FETs are of great interest nowadays. With the well-developed analyzing methodology in the project last year, we in this proposal we will further study the random-dopant-induced characteristic fluctuation in 16 nm multiple-gate FETs. In the first year, we extend our experimental and theoretical examination into diverse multiple-gate devices comprehensively, which includes single-gate silicon-on-insulator (SOI), double-gate, triple-gate SOI, triple-gate bulk, square- shaped-surrounding-gate, cylindrical-shaoed-surrounding-gate, and ellipsoidal-shaped- surrounding FETs, etc. The random dopant induced fluctuations in these devices will be calculated and compared with the TSMC characterization results. We notice that the process variation effect including the gate length derivation and line edge roughness will also be analyzied. In the second year, we will focus on development of the fluctuation suppression techniques for planar and multiple-gate FETs through the semiconductor fabrication and material engineering viewpoints, such as doping profile optimization, gate workfunction engineering and using high-κ dielectric material. Under the high performance consideration, in order to suppress the characteristic fluctuation, the most efficient approach to suppress the fluctuations for different device structure will be suggested according to device nature and intrinsic physics. Moreover, analytical formula for accurately describing the characteristic fluctuation of planar and multiple-gate devices will be derived.