針對3D整合之電子設計自動化技術開發---子計畫五：應用在驗證與測試3D IC整合過程中以計算智慧為基礎的測試向量產生方法(I)

Abstract

3D 電路設計整合提供了一個利用堆疊數層電路作為解決電路大小問題的方 法。先前的研究主要著重於解決實體層上的驗證問題，例如全域繞線、功率消 耗與電阻電容所造成的延遲效應。然而,除了3D 電路設計整合中實體層級的問 題，測試向量生成(TPG)也扮演著相當重要的角色。除了必須解決多層電路的 複雜度問題，它同時也因為電路設計不再是獨立而是相互的影響以致更複雜如 串音和時序延遲的物理現象，對於測試及驗證是更大的挑戰。 為了克服電路設計與其物理現象的高複雜度問題，一個由計算智能的學習 方法可以用來解釋由大量的模擬資料所得到電路的資訊。傳統上，電腦科學中 的學習方法的目標是為了推導出一個稱為預圖象的模型，它可以仿真電路的基 本機制，以及對於新的情況提供足夠的精確度。然而，為了加速3D 電路整合 中不同物理層級的驗證問題，雖然高準確度的要求被求被大幅的放寬了，但是 卻多了另一項向量反推(Justification)的要求。進一步來說，利用計算智能 所學習到電路的預圖象，可以由功能性的觀點找到電路設計中不足的地方，而 不必透過電路結構的分析，這將使得驗證和測試的困難被降低了。 這個計畫的第一步是要有效開發一個整合計算智能方法與有限制的決定性 測試向量產生器，以加速基於模擬資料的3D 電路整合分析。由這個架構所產 生的測試向量，可以應用在收歛分析報告中未達到的角落以及TSV 插入點的適 當位置。這個計畫最終的目標是為了要將此學習架構連結到3D 電路整合的設 計流程當中，以確保電路在經過不同層級的電路設計自動化流程後，達成期待 的效能。

Three-dimensional (3D) IC integration provides a solution capable of scaling the design complexity by stacking multiple layers of active circuits. Most of previous study has been explored various verification issues at the physical level, such as global routing, power consumption and RC delay calculation. However, on top of these physical problems during 3D IC integration, test pattern generation (TPG) also plays an important role. It is not only because integrating multiple circuits themselves incur higher complexity, but also because these designs are no longer independent and work interactively to cause more complicated physical phenomena such as crosstalk delays to challenge verification and test. To conquer the great complexity of designs and physical phenomena, learning by computational intelligence will be incorporated to reason and extract information from tremendous amount of simulation data. Traditionally, the objective of learning in computer science is to derive a model called pre-image which can mimic the behavior of the underlying mechanism and predict results with certain accuracy for a new instance. However, to facilitate various physical verification problems during 3D IC integration, the requirement of accuracy can be substantially relaxed, but a justification requirement needs to be added. With these pre-images learned from computational intelligence, design corners can be created from a functional perspective instead of analyzing the circuit structure directly, and the verification and test difficulty is therefore alleviated. The first step of this proposal is to develop a utility that integrates effective computational intelligence techniques into the constraint-based deterministic TPG methodology to facilitate the analysis of 3D IC integration on the basis of simulation data. Missing corners on coverage report and via insertions in the entire design can be verified through this framework by generating proper test patterns. The ultimate goal is to link the proposed learning framework to other design flow for 3D IC integration to help validate performances after various physical design automation processes on circuits.