異質整合Mixed-Signal/MEMS CMOS無線射頻收發機設計研發---總計畫(I)

Abstract

近年來, 在新興消費性產品帶動、製程設計產業陸續投入MEMS 微機電技術，以標 準CMOS 技術為平台實現感測器SoC 化，可實現高品質，低成本之競爭優勢，Mixed‐signal MEMS CMOS 儼然成為半導體產業革命性技術。Mixed‐signal MEMS CMOS 實為將標準 CMOS 積體電路與MEMS 充分整合的發展技術。而Mixed‐signal MEMS CMOS 採用現有 的標準化IC 製程 (CMOS process)可將微電子電路以及MEMS 微細結構以相同的設計介 面整合在一個晶片之上。為Multi‐band, Multi‐mode (MBMO) wireless transceiver 設計, 提供了極為彈性且頗具發展潛力的整合製作方法。 本計畫單位配合國家計畫主題『Heterogeneous Integration for Better Life』，開發可重 組式 Mixed‐signal/MEMS CMOS 無線射頻收發機，從事異質SoC 整合設計研發。計畫 團隊溫瓌岸教授、鄭裕庭教授及郭建男教授具有長期合作執行國科會及工研院無線射 頻接收機設計經驗，總主持人溫瓌岸教授近年參與於國科會SIPP 計畫，與鄭裕庭教授 及清華大學奈微所范龍生所長、李昇憲教授合作從事Mixed‐signal MEMS CMOS 製程及 EDA 平台開發，成果斐然，獲得多方鼓勵，李昇憲教授於去年回國，加入清華大學奈 微所，具多年RF MEMS 開發經驗，特邀請參與本計畫，藉由以Mixed‐signal MEMS 製 程及設計流程之引進，將為Multi‐band, Multi‐mode 無線射頻收發機之設計帶來諸多創 新發展方向，此係本計畫整合開發之主要原因，同時，依據現今無線通訊應用需求， 特以0.9G~10G Hz 涵概 GSM , DCS, GPS, PCS, Bluetooth, WLAN, WiMAX 及UWB 之設計 為具體技術目標。 整體分工合作架構為： 可重組式 Mixed‐signal/MEMS .9G~10GHz 射頻前端設計 可重組式 Mixed‐signal/MEMS .9G~10GHz 射頻接收端設計 可重組式 Mixed‐signal/MEMS .9G~10GHz 頻率合成器設計 可重組式 Mixed‐signal/MEMS .9G~10GHz 射頻傳送端器設計

This proposal presents a heterogeneous integration of Mixed‐signal/MEMS CMOS technology with a focus on RF applications of MEMS in the design of cellular handsets. A novel, integrated, high‐Q tunable digital capacitor is discussed to demonstrate how RF‐MEMS technology can be utilized to make high frequency components whose RF characteristics can be adjusted during operation, allowing for the first time reconfiguration of radio hardware under software control. It is concluded that as the consumer wireless market continues to grow and evolve, product designers will remain under ever increasing pressure to develop smaller, lighter, thinner products that are more functional, energy‐efficient, and intuitive, and to do so faster and at lower cost. Although issues and challenges persist, opportunities abound, and RF‐MEMS technology holds the promise of being a key enabler of future generations of more highly converged, cognitive, and flexible. The main project will cover the integrated design platform integration including device characterizations, IP library construction as will as EDA flow establishment to provide the design work to be synchronized to a single platform for easy verification and optimization. Four subprojects are included to work for the reconfigurable Multi‐mode, multi‐band RF transceiver design. The target design will be .9Ghz~10Hhz design which covers the standards including GSM , DCS, GPS, PCS, Bluetooth, WLAN, WiMAX and UWB. Job allocations for the four sub‐projects are: Sub.1 Reconfigurable mixed‐signal/MEMS CMOS front end design Sub.2 Reconfigurable mixed‐signal/MEMS CMOS receiver design Sub.3 Reconfigurable mixed‐signal/MEMS CMOS frequency synthesizer end design Sub.4 Reconfigurable mixed‐signal/MEMS CMOS transmitter design