設計、製作CMOS製程相容之微機械邏輯閘及其IC電源管理技術之應用(III)

Abstract

隨著近年來可攜式裝置（mobile devices）的盛行，其性能及續航能力的要求提高，半導體元件一 直存在的漏電流及功率損耗問題也逐漸受到重視。此一問題一直無法完全解決，因為以目前的IC 製 造技術而言，低漏電流與高效能兩者的需求相互牴觸。也由於此，試圖在兩者之間尋求平衡點的晶片 “電源管理”系統（power management）成為目前IC 設計的顯學。 由於IC元件結構的特性，傳統IC設計方式無法完全解決漏電流的問題。因此利用微波微機械切換 器（RF MEMS Switch）來改善功率消耗辦法陸續被提出。由於微機械開關完全沒有漏電流的問題， 亦無電流量不足導致效能降低的困擾，因此非常適合用來做為電源管理的控制元件。然而目前大多數 的微機械開關其僅具“開／關”功能，IC線路設計者必須更改原設計才能納入該元件，應用上受到局 限。 在本計劃預計設計、製作一符合CMOS製程的微機械邏輯閘，並將其導入電源管理系統中。此一 新式元件除了有一般微機械開關的優點外，並具有IC邏輯閘的功能，且幾乎無動態功率耗損。因此比 一般微機械開關更適合用於電源管理。在此我們提出兩種結合微機械邏輯閘與電源管理的做法，在動 態功率耗損方面：在不需更改原電路設計下，利用微機械邏輯閘直接與部分傳統的IC邏輯閘進行置 換。在靜態功率耗損管理方面：結合電源管理技術中的“功率控管”概念，利用微機械邏輯閘來管理 一個區塊的電晶體。我們預期結合微機械邏輯閘與電源管理技術，可以同時擁有一高效能與低能耗的 晶片，並廣泛應用於可攜式裝置中。 本研究已持續一年半，目前已製作出一批具“金屬-金屬接觸”且可與CMOS技術相整合的微機械 邏輯閘，但是由於薄膜的殘留應力（residual stress）過大，目前仍無法正常使用。因此，除了延續先 前規劃的電源管理系統整合技術外，本計劃將研究如何模擬、量測及控制CMOS_MEMS製程中多層結 構中的殘留應力，以提高微機電系統和超大型積體電路（VLSI）整合製程中的良率。

In current IC technology, a low leakage-current design, required for elongated uptime, inevitably leads to low bias current and slow response time of transistors. This design dilemma has been troubling IC designers for years and is getting serious with the wide spreading of mobile devices nowadays. Because of that, “power management”, a technology trying to optimize the speed and power consumption, becomes one of the most popular issues in IC designs. Because conventional IC technologies can not fully solve this problem, many researchers have proposed other solutions such as MEMS switches. These MEMS switches have the advantages of no leakage current and no tradeoff between performance and power consumption, which make themselves very good candidates for power management applications. However, most of the MEMS switches only equip with on/off function and thus, chip designers have to modify original circuits to accommodate them. This shortcoming greatly limits applications of MEMS switches. Previously, we proposed a novel device, MEMS logic gate, which not only has all the advantages of MEMS switches but also perform logic functions like IC logic gates. This electrostatically-actuated device has no leakage current and no “short-circuit current”during switching. If its fabrication process can be compatible with current CMOS technology, the proposed MEMS logic gates can directly swap with existing IC logic gates and be an even better solution for power management, as compared to other MEMS switches. In this project, we proposed designing and fabricating CMOS-compatible MEMS logic gates and two methods of integrating them in a power management system. In reducing the dynamic power consumption, we proposed, without modifying the original circuits, swapping some of the conventional IC logic gates with our MEMS logic gates. In reducing the static power consumption, we proposed using this MEMS logic gates as the “sleeping transistors”in “power gating”techniques. In this continuing research, we have fabricated the device that has the metal-to-metal contact and its fabrication process is CMOS compatible. Unfortunately, due to large residual stress, the device is not functioning properly. Thus, besides the efforts toward power management issues, we will investigate more on controlling and measuring the residual stress in thin films, in order to improve the yield of CMOS-MEMS technology.