設計、製作CMOS 製程相容之微機械邏輯閘及其IC 電源管理技術之應用 (II)

Abstract

隨著近年來可攜式裝置(Mobile devices)的盛行，其性能及續航能力的要求提高，半導體元件 一直存在的漏電流及功率損耗問題也逐漸受到重視。此一問題一直無法完全解決，因為以目前的 IC 製造技術而言，低漏電流與高效能兩者的需求相互牴觸，低漏電流的晶片設計，將直接導致低 的偏壓電流，進而造成晶片速度緩慢。也由於此，試圖在兩者之間尋求平衡點的晶片“電源管理” 系統(power management)成為目前IC 設計的顯學。 由於IC 元件結構的特性，傳統IC 設計方式無法完全解決漏電流的問題。因此利用微波微機 械切換器(RF MEMS Switch)來改善功率消耗辦法陸續被提出。由於微機械開關完全沒有漏電流的 問題，亦無電流量不足導致效能降低的困擾，因此非常適合用來做為電源管理的控制元件。然而 目前大多數的微機械開關其僅具“開／關”功能，IC 線路設計者必須更改原設計才能納入該元 件，應用上受到局限。 在本計劃預計設計、製作一符合CMOS 製程的微機械邏輯閘，並將其導入電源管理系統中。 此一新式元件除了有一般微機械開關的優點外，並具有IC 邏輯閘的功能，且幾乎無動態功率耗損。 因此比一般微機械開關更適合用於電源管理。在此我們提出兩種結合微機械邏輯閘與電源管理的 做法，在動態功率耗損方面：在不需更改原電路設計下，利用微機械邏輯閘直接與部分傳統的IC 邏輯閘進行置換。在靜態功率耗損管理方面：結合電源管理技術中的“功率控管”概念，利用微 機械邏輯閘來管理一個區塊的電晶體。 我們預期結合微機械邏輯閘與電源管理技術，可以同時擁有一高效能與低能耗的晶片，並廣 泛應用於可攜式裝置中。

In current IC technology, a low leakage-current design, required for elongated uptime, inevitably leads to low bias current and slow response time of transistors. This design dilemma has been troubling IC designers for years and is getting serious with the wide spreading of mobile devices nowadays. Because of that, “power management”, a technology trying to optimize the speed and power consumption, becomes one of the most popular research topics in IC designs. Due to the conventional IC technology can not fully solve this problem, the concept of using mechanical switches, RF MEMS switches, to solve this problem has been proposed. These MEMS switches have the advantages of no leakage current and no tradeoff between performance and power consumption, which make themselves very good candidates for power management applications. However, most of the MEMS switches only equip with on/off function and thus, chip designers have to modify their circuits in order to accommodate them. This shortcoming greatly limits their applications. Previously, we proposed a novel device, MEMS logic gate, which not only has all the advantages of MEMS switches but also it can perform logic functions like IC logic gates. This electrostatically-actuated device has no leakage current and no “short-circuit current” during switching. If its fabrication process can be compatible with current CMOS technology, the proposed MEMS devices can be directly swapped with existing IC logic gates and be an even better solution for power management, as compared to other MEMS switches. In this project, we proposed designing and fabricating CMOS-compatible MEMS logic gates and two methods of integrating them in a power management system. In reducing the dynamic power consumption, we proposed, without modifying the original circuits, swapping some of the conventional IC logic gates with our MEMS logic gates. In reducing the static power consumption, we proposed using this MEMS logic gates as the “sleeping transistors” in “power gating” techniques. We believe this CMOS-compatible MEMS logic gates technology can largely relieve the conflicts between performance and power consumptions for IC designs.