完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTsai, Hui-Wenen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:13:13Z-
dc.date.available2014-12-08T15:13:13Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1377-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/10211-
dc.identifier.urihttp://dx.doi.org/10.1109/ICECS.2007.4511221en_US
dc.description.abstractA new 2xVDD-tolerant I/O buffer circuit, realized with only 1xVDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application.en_US
dc.language.isoen_USen_US
dc.titleDesign of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradationen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ICECS.2007.4511221en_US
dc.identifier.journal2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4en_US
dc.citation.spage1240en_US
dc.citation.epage1243en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000255014801130-
顯示於類別:會議論文


文件中的檔案:

  1. 000255014801130.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。