標題: Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell
作者: Lee, Kuo-Fu
Li, Yiming
Li, Tien-Yen
Su, Zhong-Cheng
Hwang, Chin-Hong
傳播研究所
電機工程學系
Institute of Communication Studies
Department of Electrical and Computer Engineering
公開日期: 1-May-2010
摘要: In this study, a three-dimensional "atomistic" coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (sigma(SNM)) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the sigma(SNM) is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era. (C) 2010 Elsevier Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/j.microrel.2010.01.021
http://hdl.handle.net/11536/10233
ISSN: 0026-2714
DOI: 10.1016/j.microrel.2010.01.021
期刊: MICROELECTRONICS RELIABILITY
Volume: 50
Issue: 5
起始頁: 647
結束頁: 651
Appears in Collections:Conferences Paper


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