奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---總計畫

Abstract

本整合型研究計畫集合國內從事電晶體射頻與類比元件模型之專家、無線傳輸電路設計之專 家、高速連結技術之專家、高性能濾波技術之專家、高性能類比數位轉換技術之專家、以及積體電 路可靠度技術之專家，共同成立一研究團隊來從事『奈米CMOS 之高性能類比數位混合信號關鍵 電路設計技術』整合型研究計畫的研發工作，藉由各相關領域專家之合作，開發前瞻類比、射頻與 混合信號電路之各種設計核心技術，並培訓可開發各項高性能關鍵性電路之高素質研究人員與技術 人才。本整合型計畫擬針對各個關鍵性電路進行最佳化設計，因此將可依需求整合為符合各種新型 有線或無線傳輸界面之前端電路。設計完成之各高頻與高性能關鍵性電路將實際下線製作，並驗證 其性能。本整合型研究計畫之研究成果及人才培訓，對我國未來無線通訊、混合信號積體電路設計 與高性能傳輸界面設計的技術提升具有十足助益。本整合型研究計畫包含六個子計畫，分別是(1) 奈米CMOS 射頻與混合訊號模型研發應用於超低功耗與低雜訊設計；(2)極低寄生電容之靜電放電 防護技術以應用於超高速/超高頻積體電路；(3)奈米CMOS 技術之60~110-GHz 射頻前端關鍵性積 體電路研究與設計；(4)奈米CMOS 之高頻寬高線性度類比濾波器電路設計技術；(5)數位強化式類 比數位轉換技術；(6)用於高密度高速連結系統之矽光電積體電路。 本整合型研究計畫七位主持人組成共同之研究群，所有學生之座位及實驗所需之軟硬體設備 (如工作站和量測儀器)均共同使用，真正達成資源共享與密切合作，讓各子計畫的執行人員更容易 進行技術交流，並避免儀器閒置或重複採購之浪費。

This project combines the resources of several researchers to investigate the advanced high-frequency and analog circuit design in nanoscale CMOS technology, so as to promote the government policy and satisfy the industry’s need. There are 6 sub-projects in this combined project: (1) nanoscale CMOS RF and mixed-signal modeling for ultra-low power and low noise design, (2) ESD protection technique with ultra-low parasitic capacitance for ultra high-speed/high-frequency integrated circuits, (3) research and design techniques of 60-110-GHz RF front-end ICs in nanoscale CMOS technology, (4) high-speed high-linearity analog filter circuit design techniques in nanoscale CMOS technology, (5) digitally-enhanced analog-digital conversion techniques, and (6) high-speed and high-density optical transceivers. Sub-project 1 will develop enhanced device models in nanoscale CMOS technology and design ultra-low power RF front-end circuits. Sub-project 2 will develop novel ESD protection circuits with ultra-low parasitic capacitance for ultra high-speed/high-frequency circuits. Sub-project 3 will develop the key components in wireless transceiver front-end circuits using 130-nm~45-nm CMOS processes for the frequency band from 60 GHz to 110 GHz. Sub-project 4 will design high-speed high-linearity analog filters with automatic tuning circuit to compensate the process and temperature variation. Sub-project 5 will develop the calibration technique to improve ADC’s resolution and to overcome the performance limitation due to mismatches. Sub-project 6 will design the optical transceiver with high speed, high densitity, low bit error rate, and low power consumption. The topics of all the sub-projects are to develop the high-performance building blocks for advanced wireless communication and data transmission applications. In addition, the technical abilities of the graduated students will be enhanced to satisfy the need of IC design industry in Taiwan.