完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chuang Ching-Te | en_US |
dc.contributor.author | Yang Hao-I | en_US |
dc.contributor.author | Lin Yi-Wei | en_US |
dc.contributor.author | Hwang Wei | en_US |
dc.contributor.author | Shih Wei-Chiang | en_US |
dc.contributor.author | Chen Chia-Cheng | en_US |
dc.date.accessioned | 2014-12-16T06:14:07Z | - |
dc.date.available | 2014-12-16T06:14:07Z | - |
dc.date.issued | 2013-01-01 | en_US |
dc.identifier.govdoc | G11C005/14 | zh_TW |
dc.identifier.govdoc | G11C011/00 | zh_TW |
dc.identifier.govdoc | G11C007/00 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104521 | - |
dc.description.abstract | A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Data-aware dynamic supply random access memory | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 08345504 | zh_TW |
顯示於類別: | 專利資料 |