完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ker | en_US |
dc.contributor.author | Ming-Dou | en_US |
dc.contributor.author | Hsiao | en_US |
dc.contributor.author | Yuan-Wen | en_US |
dc.contributor.author | Wang | en_US |
dc.contributor.author | Chang-Tzu | en_US |
dc.date.accessioned | 2014-12-16T06:14:22Z | - |
dc.date.available | 2014-12-16T06:14:22Z | - |
dc.date.issued | 2011-02-01 | en_US |
dc.identifier.govdoc | H01L029/66 | zh_TW |
dc.identifier.govdoc | H01L023/62 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104684 | - |
dc.description.abstract | An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Electrostatic discharge protection device and related circuit | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 07880195 | zh_TW |
顯示於類別: | 專利資料 |