完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHUANG Ching-Te | en_US |
dc.contributor.author | Chen Yin-Nien | en_US |
dc.contributor.author | Hsieh Chien-Yu | en_US |
dc.contributor.author | Fan Ming-Long | en_US |
dc.contributor.author | Hu Pi-Ho | en_US |
dc.contributor.author | Su Pin | en_US |
dc.date.accessioned | 2014-12-16T06:15:00Z | - |
dc.date.available | 2014-12-16T06:15:00Z | - |
dc.date.issued | 2013-04-25 | en_US |
dc.identifier.govdoc | G11C011/40 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/105058 | - |
dc.description.abstract | The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | INDEPENDENTY-CONTROLLED-GATE SRAM | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 20130100731 | zh_TW |
顯示於類別: | 專利資料 |