標題: | Method and apparatus for solving key equation polynomials in decoding error correction codes |
作者: | Chang, Hsie-Chia Lee, Chen-Yi |
公開日期: | 3-七月-2003 |
摘要: | The presently invention discloses a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step of the error correction code decoding process whereby the polynomials are generated through at most t intermediate iterations that can be implemented with minimal amount of hardware circuitry. However, depending on the selected (N,K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of upstream data. Additionally, the present invention for computing the error locator polynomial and the error value polynomial employs an efficient scheduling of a small number of registers and finite-field multipliers (FFMs) without the need of finite-field inverters (FFIs) is illustrated. Using these new methods, a new area-efficient architecture that uses only 4t+2ρ+4 registers and three FFMs and no FFIs is presented to implement the inversionless Euclidean algorithm. |
官方說明文件#: | H03M013/00 |
URI: | http://hdl.handle.net/11536/105791 |
專利國: | USA |
專利號碼: | 20030126543 |
顯示於類別: | 專利資料 |