Bond pad design with low capacitance in CMOS technology for RF applications

doi:10.1109/LED.2006.887631

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Hsiao, Yuan-Wen	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.date.accessioned	2014-12-08T15:15:10Z	-
dc.date.available	2014-12-08T15:15:10Z	-
dc.date.issued	2007-01-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2006.887631	en_US
dc.identifier.uri	http://hdl.handle.net/11536/11396	-
dc.description.abstract	A new bond pad structure in CMOS technology with low capacitance for gigahertz radio frequency applications is proposed. Three kinds of inductors stacked under the pad are used in the proposed bond pad structure. Experimental results have verified that the bond pad capacitance is reduced due to the cancellation effect provided by the inductor embedded in the proposed bond pad structure. The new proposed bond pad structure is fully process-compatible to general CMOS processes without any extra process modification.	en_US
dc.language.iso	en_US	en_US
dc.subject	bond pad	en_US
dc.subject	capacitance	en_US
dc.subject	loss	en_US
dc.subject	radio frequency integrated circuit (RF IC)	en_US
dc.title	Bond pad design with low capacitance in CMOS technology for RF applications	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2006.887631	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	28	en_US
dc.citation.issue	1	en_US
dc.citation.spage	68	en_US
dc.citation.epage	70	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.identifier.wosnumber	WOS:000243280900023	-
dc.citation.woscount	0	-
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