標題: Latchup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test
作者: Ker, Ming-Dou
Yen, Cheng-Cheng
電機學院
College of Electrical and Computer Engineering
關鍵字: Electrostatic Discharge (ESD);system-level ESD test;power clamp circuits;board-level noise filter
公開日期: 2007
摘要: Two different on-chip power-rail electrostatic discharge (EaD) protection circuits, (1) with NMOS and PMOS feedback, and (2) with cascaded PMOS feedback have been designed and fabricated in a 0.18-mu m CMOS technology to investigate their susceptibility to system-level ESD test. The main purpose for adopting the feedback loop into the power-rail ESD clamp circuits is to avoid the false triggering during a fast power-up operation. However, during the system-level ESD test, where the ICs in a microelectronics system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a "latch-on" state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. The susceptibility of power-rail ESD clamp circuits with the additional board-level noise filter to the system-level ESD test is also investigated. To meet high system-level ESD specifications, the chip-level ESD protection design should be considered with the transient noise during system-level ESD stress.
URI: http://hdl.handle.net/11536/11457
ISBN: 978-1-4244-1349-2
期刊: 2007 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY: WORKSHOP AND TUTORIAL NOTES, VOLS 1-3
起始頁: 828
結束頁: 831
Appears in Collections:Conferences Paper