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dc.contributor.authorTseng, S. C.en_US
dc.contributor.authorMeng, C. C.en_US
dc.contributor.authorChen, W. Y.en_US
dc.date.accessioned2014-12-08T15:16:12Z-
dc.date.available2014-12-08T15:16:12Z-
dc.date.issued2006-07-06en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttp://dx.doi.org/10.1049/el:20060553en_US
dc.identifier.urihttp://hdl.handle.net/11536/12035-
dc.description.abstractTwo 50% duty cycle divide-by-3 prescalers - sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers - in the 2 pm GaInP/GaAs heterojunction bipolar transistor (HBT) technology are realised. Current switchable emitter couple logic D flip-flops are employed to form both prescalers. The proposed SHH prescaler functions up to 2.6 GHz while the SSH prescaler operates from DC to 1.75 GHz. The maximum operating frequency of the SHH prescaler is enhanced about 50% compared with that of the SSH prescaler owing to better signal synchronisation.en_US
dc.language.isoen_USen_US
dc.titleSSH and SHHGaInP/GaAs HBT divide-by-3 prescalers with true 50% duty cycleen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/el:20060553en_US
dc.identifier.journalELECTRONICS LETTERSen_US
dc.citation.volume42en_US
dc.citation.issue14en_US
dc.citation.spage796en_US
dc.citation.epage797en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000239467500010-
dc.citation.woscount2-
Appears in Collections:Articles


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