完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liang, Muh-Wang | en_US |
dc.contributor.author | Yen, Hui-Ting | en_US |
dc.contributor.author | Hsieh, Tsung-Eong | en_US |
dc.date.accessioned | 2014-12-08T15:16:17Z | - |
dc.date.available | 2014-12-08T15:16:17Z | - |
dc.date.issued | 2006-07-01 | en_US |
dc.identifier.issn | 0361-5235 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/12065 | - |
dc.description.abstract | The capability of a cobalt-phosphorous [Co(P)] layer, which was grown via the electroless plating process, to serve as the diffusion barrier of lead-tin (PbSn) solder was investigated in this work. The Auger electron spectroscopy (AES) and energy dispersive spectrometry (EDX) indicated that the phosphorous contents in Co(P) films decrease with increasing film thickness and that the average contents are no less than 8.7 at.% for the specimens prepared in this work. X-ray diffraction in conjunction with composition analyses revealed that the electroless Co(P) layer was a mixture of amorphous and nanocrystalline structures; however, the AES depth profile and subsequent analyses indicated that the first-formed Co(P) layer should be amorphous because it contains as much as 18 at.% P. This implied a good barrier capability for electroless Co(P) because, as revealed by EDX line scan, the Sn and Cu atoms could not penetrate the Co(P) layer after the PbSn/Cu/Co(P)/Cu/Ti/Si sample was subjected to annealing at 250 degrees C in a forming gas ambient for 24 h. The fact that Sn and Cu underlayers could not penetrate the Co layer after such a liquid-state annealing step was evidence that the Co(P) layer may simultaneously serve as a diffusion-barrier interlayer dielectric and as an under-bump metallization for flip-chip copper (Cu) ICs. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | electroless plating | en_US |
dc.subject | cobalt-phosphorous | en_US |
dc.subject | diffusion barrier | en_US |
dc.title | Investigation of electroless cobalt-phosphorous layer and its diffusion barrier properties of Pb-Sn solder | en_US |
dc.type | Article | en_US |
dc.identifier.journal | JOURNAL OF ELECTRONIC MATERIALS | en_US |
dc.citation.volume | 35 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | 1593 | en_US |
dc.citation.epage | 1599 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000239159200014 | - |
dc.citation.woscount | 16 | - |
顯示於類別: | 期刊論文 |