以無電電鍍技術沉積鈷磷合金應用於銲錫擴散阻障層之研究

Abstract

本實驗以無電電鍍沉積技術（Electroless Plating）在矽晶片基板上製作無電電鍍鈷磷（Co-P）合金薄膜，再以電鍍方式沉積錫鉛（Pb-Sn）銲料於其上，用以探討無電鍍鈷磷薄膜做為銅製程覆晶接合（Flip-chip Bonding，FC）凸塊底部金屬化（Under Bump Metallurgy，UBM）之應用可行性。將表面鍍有鈦/銅（Ti/Cu）金屬層之矽晶片基板浸置於無電鍍鈷鍍浴300秒可獲得厚度約600 nm之鍍層，由歐傑電子能譜儀（Auger Electron Spectroscopy，AES）及能量散佈光譜儀（Energy Dispersive Spectrometer，EDX）之元素成分分析結果顯示，鈷膜中之磷含量隨其厚度之增加而降低，但鍍成之鈷膜平均磷含量皆高於10 at.%；X光繞射（X-ray Diffraction，XRD）分顯示無電鍍鈷膜主要應由奈米微晶（Nano-crystallinity）組成。掃描式電子顯微鏡（Scanning Electron Microscopy，SEM）亦被使用以觀察無電鍍鈷磷層與錫鉛銲錫之界面反應，在250□C、氮氣環境下之熱處理中，介金屬化合物的厚度隨著時間的增加而增加，當熱處理至6小時以上，介金屬化合物的形成則趨於緩和。元素線掃描分析結果顯示，在錫、銅及鈷之相互擴散反應過程中，當做為潤濕層的銅完全被消耗掉之後，錫仍只在鈷磷鍍層與銲錫的界面處；經250□C、24小時之熱處理後，錫無法穿透鈷磷層的阻擋，而底層的銅亦無法擴散之銲錫層中，故證實無電鍍鈷磷層可同時做為銅製程之銅導線與銲錫凸塊之擴散阻障層（Diffusion Barrier），而其阻擋能力主要由高磷含量之初鍍鈷層形成之非晶質結構所提供。

Electroless plating technique was utilized to prepare the cobalt-phosphorous (Co-P) thin film to serve as the diffusion barrier layer of lead-tin (Pb-Sn) solder. Co-P/solder interfacial reactions were characterized in order to evaluate the feasibility of electroless Co-P layer as the under bump metallurgy (UBM) for flip-chip bonding. After depositing Ti/Cu layer on Si wafer, we immersed the samples in the electroless plating bath for 5 min to obtain the Co-P layer with thickness about 600 nm. The analyses using Auger electron spectroscopy (AES) and energy dispersive spectrometer (EDX) indicated that the phosphorous contents in Co-P films decreases with the increase of film thickness and the average contents are higher than 10 at.% for the specimens prepared in this work. X-ray diffraction (XRD) analysis revealed that the electroless Co-P layers are nanocrystalline granular structure. Cross-sectional scanning electron microscopy (SEM) was adopted to examine the interfacial reactions of electroless Co-P layer and Pb-Sn solder. For the samples annealed at 250□C in N2 ambient, the thickness of intermetallic compounds (IMCs) at Co-P/solder interface increased with the time of thermal treatment. However, there was no distinct raise of thickness of IMCs after 6-hr annealing. The EDX line scan analysis revealed that during the interdiffusion of Sn, Cu, and Co, the Sn remains at the interface of Co-P layer after the Cu wetting layer was totally consumed. The fact that Sn and Cu underlayer could not penetrate Co-P layer after 250□C, 24-hr annealing evidenced that the Co-P layer may serve as a good diffusion barrier of UBM structure for both Cu interconnect and solder bumping for Cu-ICs. The excellent diffusion retardation ability of Co-P should result from the amorphous nature provided by the high-phosphorous content in Co layer.