標題: Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction
作者: Lin, Chia-Pin
Tsui, Bing-Yue
Hsieh, Chih-Ming
Huang, Chih-Feng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2007
摘要: Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction were fabricated. Symmetric threshold voltage was obtained by implant-to-silicide technique. Lateral growth rate and thermal stability of NiSi on SiO2 were investigated. Single silicide and low temperature process make the proposed process very promising in sub-45nm technology nodes.
URI: http://hdl.handle.net/11536/12357
ISBN: 978-1-4244-0584-8
期刊: 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Proceedings of Technical Papers
起始頁: 172
結束頁: 173
Appears in Collections:Conferences Paper