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dc.contributor.authorChou, Fang-Tingen_US
dc.contributor.authorHung, Chung-Chihen_US
dc.date.accessioned2015-07-21T11:20:54Z-
dc.date.available2015-07-21T11:20:54Z-
dc.date.issued2014-01-01en_US
dc.identifier.issn1349-2543en_US
dc.identifier.urihttp://dx.doi.org/10.1587/elex.11.20140572en_US
dc.identifier.urihttp://hdl.handle.net/11536/124164-
dc.description.abstractA compact and low-power design of a 12-bit binary-weighted current-steering DAC is presented. Instead of 4096 unit current cells, the proposed design uses 192 unit current sources with two reference currents. The silicon area of the generation circuit of two reference currents is very compact as well. The area of the total current source arrays is smaller than four times the area of 6-bit current source arrays, which has significantly reduced the dimension of the analog part of a conventional 12-bit DAC. The proposed DAC achieves 400 MS/s update rate and consumes 38.7 mW from single 1.8 V supply.en_US
dc.language.isoen_USen_US
dc.subjectdigital-to-analog converteren_US
dc.subjectDACen_US
dc.subjectcompact areaen_US
dc.titleA compact 12-bit DAC with novel bias schemeen_US
dc.typeArticleen_US
dc.identifier.doi10.1587/elex.11.20140572en_US
dc.identifier.journalIEICE ELECTRONICS EXPRESSen_US
dc.citation.volume11en_US
dc.citation.issue17en_US
dc.contributor.department電機資訊學士班zh_TW
dc.contributor.departmentUndergraduate Honors Program of Electrical Engineering and Computer Scienceen_US
dc.identifier.wosnumberWOS:000344925800011en_US
dc.citation.woscount0en_US
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