標題: A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement
作者: Chiu, Chao-Chang
Huang, Po-Hsien
Lin, Moris
Chen, Ke-Horng
Lin, Ying-Hsi
Tsai, Tsung-Yen
Lee, Chen Chao-Cheng
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: Current efficiency;digital low dropout (DLDO) regulator;resistance-locked loop (RLL)
公開日期: 1-一月-2015
摘要: The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
URI: http://dx.doi.org/10.1109/TCSI.2014.2342380
http://hdl.handle.net/11536/124227
ISSN: 1549-8328
DOI: 10.1109/TCSI.2014.2342380
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 62
起始頁: 59
結束頁: 69
顯示於類別:期刊論文