標題: | Memory-efficient architecture for JPEG 2000 coprocessor with large tile image |
作者: | Wu, BF Lin, CF 電控工程研究所 Institute of Electrical and Control Engineering |
關鍵字: | code-block;discrete wavelet transform (DWT);embedded block coding (EBC);JPEG 2000;quad code-block (QCB);tile size |
公開日期: | 1-四月-2006 |
摘要: | The experimental results show that using a larger the size to perform JPEG 2000 coding results in better image quality (i.e., greater than or equal to 256 x 256 tile image). However, processing large tile images also requires relatively high memory for the hardware implementation. For example, it would require tile memory of 256 K words to support the process of a 512 x 512 tile image in the straightforward architecture. To reduce hardware resources, we have proposed the quad code-block (QCB) -based discrete wavelet transform method to reduce the size of tile memory by a factor of 4. In this paper, the remaining 1/4 tile memory can be further reduced through two approaches: the zero-holding extension with slight image degradation and the QCB-block size extension without any image degradation. That is, it only requires 12 K words tile memory to support the process of 512 x 512 tile image by using zero-holding extension, and 13.58 K words memory through QCB-block size extension. The low memory requirement makes the on-chip memory practicable. |
URI: | http://dx.doi.org/10.1109/TCSII.2005.862042 http://hdl.handle.net/11536/12449 |
ISSN: | 1057-7130 |
DOI: | 10.1109/TCSII.2005.862042 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Volume: | 53 |
Issue: | 4 |
起始頁: | 304 |
結束頁: | 308 |
顯示於類別: | 期刊論文 |