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dc.contributor.authorSu, Hung-Chengen_US
dc.contributor.authorWu, Tsung-Hanen_US
dc.contributor.authorTsai, Chun-Jenen_US
dc.date.accessioned2015-07-21T08:31:16Z-
dc.date.available2015-07-21T08:31:16Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-3432-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/124907-
dc.description.abstractIn this paper, we presents the design of a hardware temporal multi-threading architecture for a Java processor. The Java virtual machine (JVM) model is a stack machine where the process state is the snapshot of the Java stack If the runtime stack is stored (or cached) in on-chip memory for performance reasons, the backup and restoration of the Java runtime stacks for context switching would be expensive operations. We propose a Ping-Pong buffer architecture in this paper to facilitate fully hardware-based multi-threading capability for a Java processor. The proposed hardware architecture has been implemented and verified on an FPGA platform, Xilinx ML605. The experimental results show that the proposed context-switching efficiency is much higher than that of a software-based VM such as the CVM-JIT. Therefore, the proposed hardwired Java processor is promising for embedded applications that require heavy multi-threading operations.en_US
dc.language.isoen_USen_US
dc.subjectJAVA PROCESSORen_US
dc.subjectTEMPORAL MULTITHREADINGen_US
dc.subjectEMBEDDED SYSTEMSen_US
dc.titleTemporal Multithreading Architecture Design for a Java Processoren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage2201en_US
dc.citation.epage2204en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000346488600552en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper