標題: | A Dual-Level Dual-Phase Pulse-Width Modulation Class-D Amplifier with 0.001% THD, 112 dB SNR |
作者: | Yang, Shang-Hsien Yang, Yuan-Han Chen, Ke-Horng Hung, Chung-Chih Wey, Chin-Long Lin, Ying-Hsi Tsai, Tsung-Yen Huang, Chen-Chih Lee, Chao-Cheng Tai, Zhih Han Cheng, Yi Hsuan Tsai, Chi Chung Luo, Hsin-Yu Wang, Shih-Ming Chen, Long-Der Yang, Cheng-Chen Hui, Huang Tian 資訊工程學系 Department of Computer Science |
關鍵字: | Class-D;dual-level dual-phase PWM;THD |
公開日期: | 1-一月-2014 |
摘要: | this paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180 degrees out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV. |
URI: | http://hdl.handle.net/11536/124909 |
ISBN: | 978-1-4799-3432-4 |
ISSN: | 0271-4302 |
期刊: | 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 2676 |
結束頁: | 2679 |
顯示於類別: | 會議論文 |