標題: Method for Resolving Simultaneous Same-Row Access In Dual-Port 8T SRAM with Asynchronous Dual-Clock Operation
作者: Lien, Nan-Chun
Chuang, Ching-Te
Wu, Wen-Rang
電機資訊學士班
電子工程學系及電子研究所
Undergraduate Honors Program of Electrical Engineering and Computer Science
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2013
摘要: This work proposes a novel Dual-Port (DP) 8T SRAM operation scheme. The scheme improves the Read stability and Write-ability, and allows asynchronous operation with arbitrary clock timing skew between two ports. It facilitates high performance, low-power and low VM1N with minimum device and area overhead. Postsimulation results show almost no timing penalty for simultaneous same-row access and the performance is almost the same as that for one port operation.
URI: http://hdl.handle.net/11536/125066
ISBN: 978-1-4799-1166-0
ISSN: 2164-1676
期刊: 2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC)
起始頁: 105
結束頁: 109
Appears in Collections:Conferences Paper