標題: A 0.1-3GHz Cell-Based Fractional-N All Digital Phase-Locked Loop Using Delta Sigma Noise-Shaped Phase Detector
作者: Liu, Yao-Chia
Chen, Wei-Zen
Chou, Mao-Hsuan
Tsai, Tsung-Hsien
Lee, Yen-Wei
Yuan, Min-Shueh
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: TDC;Delta Sigma phase detector;fractional-N ADPLL
公開日期: 1-Jan-2013
摘要: A 0.1-3 GHz, cell-based, fractional-N ADPLL with Delta Sigma noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um x 240um.
URI: http://hdl.handle.net/11536/125071
ISBN: 978-1-4673-6146-0
ISSN: 
期刊: 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)
Appears in Collections:Conferences Paper