針對奈米積體電路之時序分析與最佳化

Abstract

在現今積體電路設計流程中，時序分析與最佳化是兩個不可或缺的程序。時序分析藉由計算電路延遲時間、檢查時序限制以及找出最差時序關鍵路徑來驗證積體電路設計之時序效能；而時序最佳化藉由修正最差時序關鍵路徑、找出可運行之工作時脈等方式來達成時序收斂之目的。然而，進入奈米積體電路世代後，急遽增加的積體電路晶片設計複雜度及快速成長的製程變異使得時序分析與最佳化面臨許多新的挑戰。 為了加速計算，現有的時序分析以正反器為邊界，將一個電路分割成一些時序路徑，再獨立地計算各個時序路徑之延遲時間及驗證其時序效能。步入奈米設計世代後，對於多個相連的時序關鍵路徑（關鍵相依路徑），獨立計算與驗證的方法可能產生過於樂觀的結果。另外，為了確保電路時序在最差情況下可以正常運作，在計算一條時序路徑之延遲時間時，通常對於資料出發正反器的時脈路徑與資料接收正反器的時脈路徑會採用不同的製程變異條件，但是在出發路徑與接收路徑的共同路徑上的邏輯閘不可能同時處在兩個不同的變異條件上，因此這個方法會產生不自然卻無法避免的悲觀時序分析結果（共同路徑悲觀性）。另外一方面，在時序最佳化中，保持時間修正在電路設計流程中是一個必要的步驟。然而，保持時間修正在高速電路設計中的時序錯誤自我回復電路上更加困難。在本篇論文中，我們針對這些新的挑戰提出新穎的解決方法。 為了消除在關鍵相依路徑上所產生之過於樂觀結果，我們先提出一個簡單且有效率的三角時序模型來描述關鍵相依效應，再利用三角時序模型，我們提出一個考慮關鍵相依效應之靜態時序分析方法，而且所提出之方法可以與當前通用的時序分析流程結合。而針對共同路徑悲觀性，我們利用區域性靜態時序分析與分支限定演算法，建立一個移除共同路徑悲觀性的時序分析流程，在分支限定演算法中，我們更進一步提出時序模型圖化簡、動態邊界調整以及平行運算來加速路徑追蹤流程。 另一方面，針對時序錯誤自我回復電路，我們提出一保持時間修正演算法來修補所產生之嚴重的短路徑問題，為了縮短時序錯誤自我回復電路設計流程，我們建立一預先適性分析方法來制定時脈頻率；不同於前人使用的狹隘性貪婪演算法，我們提出可全域性考慮修補延遲量及修補位置之演算法；再者，我們利用可提供離散延遲時間的備用元件，及可提供大量與可調整電容的填補金屬，於晶片布局設計後期階段，完成所要求填補之延遲。

Timing analysis and optimization are two crucial processes in the modern IC design flow. Timing analysis verifies the timing performance of a design by calculating the circuit delay, checking timing constraints, and identifying timing critical paths, while timing optimization achieves timing closure of a design through improving identified timing critical paths, determining operable clock frequencies, etc. However, with rapidly growing design complexities and increasing on-chip variations, timing analysis and optimization encounter new design challenges. To facilitate the computation, conventional timing analysis divides a design into sets of timing paths blocked by flip-flops and then performs delay calculation and timing verification on each timing path independently. For nanometer design, the independent analysis may generate over-optimistic results on consecutive critical paths (i.e., criticality-dependent paths). In addition, to guarantee the timing performance under worst-case conditions, conventional timing analysis applies different operating conditions on the launch and capture clock paths during delay calculation. Thus, the conventional analysis induces artificially pessimistic results on the common part of the launch and capture clock paths (i.e., common path pessimism). On the other hand, for timing optimization, hold time fixing is an essential step for achieving timing closure in the design flow. Nevertheless, this task becomes much severer in timing error resilient circuits for high performance design, which eliminate a conservative timing guardband by error detection and correction. In this dissertation, we propose novel solutions to overcome these challenges. For eliminating the over-optimism on the criticality-dependent paths, in this dissertation, we first propose a simple yet effective triangle model to characterize the criticality-dependency effect. Then, we devise a criticality-dependency-aware static timing analysis flow, which is seamlessly integrated with the common timing analysis flow. For removing the common path pessimism on clock paths, instead of exhaustive exploration on all paths in a design, we propose a timing analysis framework considering common path pessimism removal based on block-based static timing analysis and branch-and-bound. Along with the branch-and-bound mechanism, we further propose timing graph reduction, dynamic bounding and parallel computing to speed up the path retrieval. On the other hand, we develop a hold time fixing (shortest path padding) framework to enable the timing error detection and correction mechanism of resilient circuits. To shorten the resilient circuit design process, we first propose a feasibility checking criterion to determine the target clock period. Unlike greedy heuristics with a local view adopted by recent prior work, we determine the padding values and locations with a global view. Moreover, we utilize spare cells, offering the amount of discrete delay, and the dummy metal, offering an abundant and tunable resource of capacitance, to achieve the derived padding values at the post-layout stage.