敏捷類比電路合成與佈局設計遷移方法

Abstract

在積體電路的範疇,為了更有效地達到先進製程底下的電路效能,類比電路的自動 化已不容忽視。再更深入地探討類比電路合成以及佈局設計自動化,有條件性地電路 設計將變得更為重要。當我們探討類比電路合成時,元件模型、效能需求以及寄生電 容效應構成了探索電路方程式的限制條件。然而,清楚掌握電路元件的非線性方程式 也同樣十分複雜與耗時。除此之外,由於電路的效能對於實體佈局設計也相當敏感, 佈局相依效應在佈局設計時也需要一併考慮。傳統上,佈局設計為了能夠滿足生產的 電路效能需求,大多仰賴曠日費時的人工調整。更甚者,隨著先進製程的演進,元件 模型的複雜度以及佈局設計的限制條件也不斷提升。倘若與設計相依的限制條件能在 自動化合成與佈局設計的同時被重視,先進製程底下類比電路的困難度也會隨之減緩。 在這篇論文中,我們提出了一套從電路合成到佈局設計產生的類比電路遷移設計演 算法。該套件可被拆分為三個階段,基於平行化基因演算法的電路效能探索、基於整 合性限制條件的類比電路繞線以及類比電路敏捷佈局遷移雛形開發。為了滿足遷移設 計所要實現的內容,目標製程的電路合成以及實體佈局產生都需要被一一實踐。首先, 基於平行化基因演算法的效能探索可以分析出特定積體電路製程底下的設計極限。我 們所提出的方法不只是逐一檢視在各個設計邊界的特性,基因演算法勾勒出該製程的 效能區間供最佳化設計。實驗結果展現了我們的基因演算法以及機率分布式的電路模 擬。我們所提出的效能探索可以有效且迅速地在射頻分散式放大器以及運算放大器基 於不同製程下找到效能極限並設計之。 接著我們提出了一個整合式限制條件的類比電路繞線方法,該方法提供了一個整合 電路的設計限制以及製程限制的概念以實現業界等級的電路設計產品。事實上,大部份的設計限制條件經由積體電路製造商所提供的僅限於在實體佈局上的限制條件,該 條件並未實際考慮由前端電路設計提供之設計條件。然而,這些設計限制相當地重要。 為了實現實體佈局電路設計自動化,我們提出了整合性設計限制條件組合。同時我們 也將這個概念實際運用在 tsmc 的 40 奈米製程電路上。該電路由於保存了前端設計的 限制條件,線路的對稱性提升了電路的訊號穩定性。我們同時也測試了不同的限制條 件對於繞線的順序造成了電路效能的顯著影響。 最後,我們在論文中提出了一種敏捷的類比電路設計遷移方法。在先進製程中,由 於設計限制條件倍增以及效能需求倍增,類比電路自動化逐漸變得更複雜。不僅如此, 寄生電路效應嚴重以及製造可靠性不確定讓情況變得更加複雜。為了有效參考現有的 電路設計,我們提出的電路遷移方法能夠萃取不只是佈局擺放特性,也保存了繞線與 佈局擺放之間的關聯性。讓遷移設計時的繞線擺放更為簡單與有依據。除此之外,由 於佈局擺放的彈性增加,我們的遷移方法可以產生多組的雛形設計以供選則。不僅如 此,該遷移方法也能針對設計中的每一條繞線調整最佳化。實驗結果展現了產生多組 佈局設計結果的可行性,在不影響整體電路效能的前提下,也有效提升了自動化繞線 的完成度。 總而言之,我們的類比電路遷移設計演算法,實現了在先進製程底下從電路合成到 佈局雛形產生類比電路並符合需求,同時我們的實驗結果也展示了我們所提出方法的 正確性與效率。

Analog design automation has become one of the most important issue to efficiently achieve design specification in integrated circuit industry. To work on this issue, constraint- driven design generation plays a key role in analog circuit synthesis and layout generation. During circuit synthesis, device models, performance specification and parasitics’ effects consolidate the constraints for exploring the design equation. Yet, to figure out the set of non-linear design equations is complicated and time-consuming. Meanwhile, in layout generation stage, the layout dependent effect (LDE) should be taken into consideration since the performance of analog design is sensitive to physical layout constraints. Traditional layout strategy with manual manipulation requires tremendous time to satisfy specification for sign-off. Moreover, as technology node advances, the complexity of device models and layout constraints is increased as well. The hardship of realization analog circuit on advanced technology node can considerably drop off if the constraints corresponding to design are treated well during synthesis and layout generation. In this dissertation, we propose an analog design migration framework, which com- prehensively generates analog design from synthesis to layout. The migration strategy is divided into 3 phases: parallel genetic performance exploration for circuit sizing, unified constraint-driven routing for analog layout and rapid prototyping for analog layout migration. To satisfy the migration purpose, both circuit synthesis and layout generation on targeting technology should be satisfied. Our parallel genetic performance exploration analyzes the limitation of a specific technology via genetic algorithm efficiently. Other than examining the corners of device model carefully, genetic algorithm provides a sketch of performance space to explore. Experimental results show that the integration of our genetic performance exploration and probabilistic perturbation achieves both efficiency and accuracy on a radio-frequency distributed amplifier (RFDA) and a folded cascode operational amplifier (Op-Amp) in three different technologies. The second approach, unified constraint-driven routing, provides an integration concept of generating constraints for industrial analog designs. Most of the layout constraints provided by manufacturing foundries are technology-oriented. However, the design constraints provided by designers are critical as well. We propose an unification of technology and design constraints to perform layout generation. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact. In our last approach of this dissertation, a rapid layout migration for analog circuit is presented. Layout generation for analog design in advanced CMOS technology is challenging due to growing layout constraints and performance specifications. The manufacturing reliability and parasitic effects make the situation more severe. To facilitate the utility of template-based analog layout generation is solving such problem, our migration approach extracts both placement and routing from an existing layout and then implements rapid prototyping to generate multiple results. In addition, the wires in the resulting layout are optimized for better performance. The experimental results demonstrate the possibility on multiple layout migration, such that more than 75% routing of migrated layout is generated with qualified performance. In all, our migration framework achieves the requirement to generate analog design in advanced technologies from synthesis to layout prototypes, and the experimental results have demonstrated the efficiency and accuracy of all three proposed methodologies.