建構可調變觸發電壓與維持電壓的堆疊型矽控整流器應用於高壓箝位電路之靜電放電防護

Abstract

在我們日常生活中，靜電放電隨處可見，而元件的靜電放電防護能力卻因為隨著製程技術的進步大幅下降。如果使用LDD(源極輕摻雜)結構的元件，在1μm的尺寸時以人體放電模型規格來看，耐壓降到了只剩下不到2000V，這會使得元件容易因為靜電放電的電流過大而遭到破壞。所以我們這次實驗的主要目的是建構一個靜電電流防護元件，使其能夠有效的保護積體電路內的元件避免毀壞。首先我們會探討矽控整流器的特性，包含基本的電流電壓特性、崩潰機制、以及崩潰機制有關的重要參數。根據以上的討論，我們提出一些辦法來有效的抑制閂鎖效應 (latch-up effect)的產生，還有矽控整流器是否能夠在積體電路內的元件崩潰前及時開啟的議題，使得矽控整流器能夠操作在一個有效的區間來防止靜電放電帶來的負面效應。 論文中另一個部分會討論到，如果如何將矽控整流器應用在高壓電路中。因為高壓電路的操作電壓大約在30V，但是矽控整流器的維持電壓 (holding voltage)會因為驟回現象 (snapback effect)而過低，所以我們會在第二章與第三章時提出如何解決維持電壓過低的問題，使其得以在高壓電路中使用。

In our daily lives, electrostatic discharge can be seen everywhere. However, the ESD protection capability of device is decreased with the progress of process technology. For example, in human body model, the ESD protection capability of device with LDD structure is lower than 2000V in feature size equal to 1μm. Hence, the device will be destroyed easily by ESD. In this thesis, our propose is to make a ESD protection device to protect the internal circuit of ICs. First, we will engage in the characteristic of SCR, include the I-V curve discussion, the breakdown mechanism, and some of the key specific parameters related to breakdown voltage. According to the above discussion, we propose some advices to prevent the issue of latch-up. Another part of our study is to apply SCR into HV-ICs. The operating voltage of HV-ICs is equal to 30V. We will face the challenge to apply SCR into HV-ICs because the phenomenon of snapback will reduce the holding voltage of SCR. We will propose some advices to increase the holding voltage of SCR to make it can be used in HV-ICs.