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dc.contributor.author陸廣湖en_US
dc.contributor.authorLuc, Quang-Hoen_US
dc.contributor.author張翼en_US
dc.contributor.authorChang, Edward-Yien_US
dc.date.accessioned2015-11-26T01:02:47Z-
dc.date.available2015-11-26T01:02:47Z-
dc.date.issued2015en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT070081527en_US
dc.identifier.urihttp://hdl.handle.net/11536/127652-
dc.description.abstract高介電質閘極氧化物與三五族複合材料的介面特性一直阻礙著未來先進互補式金屬氧化物半導體(CMOS)的元件微縮。本篇博士論文主要是在討論閘極氧化物與砷化銦鎵材料介面的鈍化效應,並且藉由不同類型的表面處理方式以達到高效能的三五族砷化銦鎵場效電晶體。 介電質成長後熱退火(PDA)及金屬後熱退火(PMA)製程將會嚴重地影響鉑/三氧化二鋁/砷化銦鎵(Pt/Al2O3/In0.53Ga0.47As)結構的金氧半導體電容(MOSCAP)特性。長時間且高溫的熱退火製程,會導致金屬擴散至閘極氧化物中,而使元件降低其元件特性表現。此外,藉由氫氣與氮氣混合氣體環境下退火,可以提升三氧化二鋁與砷化銦鎵(Al2O3/In0.53Ga0.47As)介面特性。 本篇論文解釋了沉積氧化物前化學溶液鈍化處理與樣品送入原子層沉積系統(Atomic Layer Deposition)之間所經過的時間(Q-time),三氧化二鋁與砷化銦鎵介面品質將受到樣品與空氣接觸的時間之影響。在比較不同的時間(Q-time)後,各種化學溶液與dry TMA成長前處理的樣品中發現類似的電容電壓(C-V)電性圖。這說明了Q-time其實不是影響高介電質氧化物與三五族材料介面品質的主要原因。換句話說,形成介面缺陷的主要原因,不僅僅是因為原生氧化層,主要因素包含了三五族材料本身自體缺陷以及原子的不完全鍵結。 為了得到更高品質的三氧化二鋁與砷化銦鎵介面特性,本篇論文研究中使用了增強型電漿原子沉積系統所成長的氮化鋁(PEALD-AlN)介面鈍化層,並且討論了不同電漿強度下的特性表現。利用150瓦特的電漿強度下成長氮化鋁介面鈍化層,N型和P型的砷化銦鎵金氧半導體元件皆得到卓越電性特性。本實驗更進一步使用了X射線光電子能譜分析儀(XPS)以及高解析度穿透式電子顯微鏡(HRTEM)分析三氧化二鋁與砷化銦鎵介面特性。 透過二氧化鉿/砷化銦鎵(HfO2/In0.53Ga0.47As)金氧半導體元件,研究氮化鋁鈍化層介面特性,得到卓越的電性表現,其中包含:強反轉型電性表現、unpinned Fermi level、低密度介面缺陷。二氧化鉿/氮化鋁/砷化銦鎵(HfO2/AlN/In0.53Ga0.47As)結構的能帶分析已扣除了價帶差值2.81±0.1電子伏特(eV)和導帶差值1.9±0.1電子伏特(eV)。使用閘極介電質沉積後電漿處理法,可以更進一步鈍化三五族介面,並得到優化的閘極氧化物品質。本篇論文使用二氧化鉿/氮化鋁/砷化銦鎵金氧半導體電容元件,得到奈米以下等級的等效氧化層厚度(EOT),並且有效的降低漏電流和介面缺陷。 本實驗使用增強型電漿原子沉積系統之相關鈍化處理方法,應用在二氧化鉿/砷化銦鎵(HfO2/In0.53Ga0.47As)金氧半導體電晶體。結合閘極氧化物前處理的氮化鋁介面鈍化層(PEALD-AlN)以及成長介電質後電漿處理方法,使之閘極堆疊類型得到極佳的特性表現。其電晶體電性表現在最高汲極電流(IDSmax)、轉導(Gm)特性、次臨界擺幅(Subthreshold Swing)、漏電流、等效電子遷移率上都有顯著的進步。此外,在X射線光電子能譜分析儀(XPS)量測金氧半電容元件的分析結果中,發現使用鈍化處理後的銦原子、鎵原子相關的本質缺陷鍵結訊號明顯得降低,說明了介面缺陷的改善,這也證明了此氧化物與三五族材料介面間的卓越高品質。換句話說,本論文所提及的閘極介電質處理方式適用於二氧化鉿/砷化銦鎵(HfO2/In0.53Ga0.47As)介面,並且也在其閘極堆疊方式的三五族金氧半場效電晶體中得到電性表現上卓越的進步。zh_TW
dc.description.abstractFuture evolution of complementary metal oxide semiconductor (CMOS) downsizing has long been hindered by the unexpected interface quality between the high-k materials and III-V compound semiconductors. This dissertation aims on the passivation of high-k/In0.53Ga0.47As structures by various surface treatments to realize high performance In0.53Ga0.47As-based MOS devices. The characteristics of Pt/Al2O3/In0.53Ga0.47As MOS capacitors (MOSCAPs) are strongly affected by post deposition annealing (PDA) and post metallization annealing (PMA) processes. Long PMA duration at high temperature has resulted in the degradation of electrical properties, associating with the out-diffusion of metal into oxide layer. The marked improvement on the Al2O3/InGaAs interface is observed with PDA process in forming gas (FG) ambient. Impact of atmosphere exposure duration between extrinsic chemical treatment and atomic layer deposition (ALD) chamber loading (Q-time) on the quality of the Al2O3/p-In0.53Ga0.47As interfaces are illustrated. For different Q-times, similar capacitance-voltage (C-V) behaviors of Al2O3/p-In0.53Ga0.47As MOSCAPs have been obtained with the use of various chemical solutions and dry TMA pretreatment. It means Q-time is not the critical parameter specifying high-k/III-V interface quality. Furthermore, the appearance of interface trap states could be mainly attributed to the InGaAs native defects and dangling bonds instead of the native oxides. The use of plasma enhanced atomic layer deposition (PEALD) AlN, with various plasma powers, for better quality of Al2O3/In0.53Ga0.47As interfaces are studied. Excellent C–V behaviors are obtained on both types of In0.53Ga0.47As MOS devices by employing a thin AlN interfacial passivation layer prepared at the plasma power of 150 W. X-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy (HRTEM) analyses have been conducted to examine the Al2O3/AlN/In0.53Ga0.47As interface. Influences of PEALD-AlN have been characterized on the HfO2/In0.53Ga0.47As MOS devices. Strong inversion behaviors, unpinned Fermi level, and low density of trap states (Dit) confirm outstanding quality of AlN interfacial layer. The band alignment of HfO2/AlN/In0.53Ga0.47As structure with the valence band offsets of 2.81 ± 0.1 eV and the conduction band offsets of 1.9 ± 0.1 eV have been deducted. Using post remote-plasma treatment in an in situ ALD process, further passivation on III-V surface and optimized high-k dielectric quality are obtained. Sub-nanometer EOT HfO2/AlN/In0.53Ga0.47As MOS capacitors with low Dit and low leakage current have been achieved. The enhanced performance n-channel inversion-mode HfO2/In0.53Ga0.47As MOSFET has been demonstrated using in situ PEALD passivation processes. The combination of PEALD-AlN as pre-gate treatment and post-gate treatment with remote-plasma gas has allowed the achievement of distinguished dielectric gate stack quality. This is associated by the improvements on the maximum drain current, maximum transconductance peak, subthreshold swing, off leakage current, and effective electron mobility. Low Dit obtained with MOSCAP is accordance with the suppression of In- and Ga-related signals from XPS analysis. It indicates a very high interfacial quality of high-k/III-V structure has been achieved. In other words, the optimization at the HfO2/In0.53Ga0.47As interface is favorable to the marked improvement on the MOS field effect transistor performance.en_US
dc.language.isoen_USen_US
dc.subjectMOSCAPzh_TW
dc.subjectMOSFETzh_TW
dc.subjectAlNzh_TW
dc.subjectAl2O3zh_TW
dc.subjectHfO2zh_TW
dc.subjectMOSCAPen_US
dc.subjectMOSFETen_US
dc.subjectAlNen_US
dc.subjectAl2O3en_US
dc.subjectHfO2en_US
dc.title高介電質與三五族之介面活性層在互補式金屬氧化層半導體之應用zh_TW
dc.titlePASSIVATION OF HIGH-K/III-V INTERFACES FOR POST CMOS APPLICATIONen_US
dc.typeThesisen_US
dc.contributor.department材料科學與工程學系所zh_TW
Appears in Collections:Thesis