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dc.contributor.authorHe, Wen-Quanen_US
dc.contributor.authorChen, Yuan-Hoen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2015-12-02T02:59:17Z-
dc.date.available2015-12-02T02:59:17Z-
dc.date.issued2015-08-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2015.2440731en_US
dc.identifier.urihttp://hdl.handle.net/11536/128006-
dc.description.abstractThis study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-mu m CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.en_US
dc.language.isoen_USen_US
dc.subjectBooth encoderen_US
dc.subjectdynamic error-compensationen_US
dc.subjectfixed-width multiplieren_US
dc.subjectmathematical probable modelen_US
dc.titleHigh-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2015.2440731en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume62en_US
dc.citation.spage2052en_US
dc.citation.epage2061en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000358616100017en_US
dc.citation.woscount0en_US
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