Improved Multi-level Control of RRAM Using Pulse-Train Programming

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Zhao, Liang	en_US
dc.contributor.author	Chen, Hong-Yu	en_US
dc.contributor.author	Wu, Shih-Chieh	en_US
dc.contributor.author	Jiang, Zizhen	en_US
dc.contributor.author	Yu, Shimeng	en_US
dc.contributor.author	Hou, Tuo-Hung	en_US
dc.contributor.author	Wong, H. -S Philip	en_US
dc.contributor.author	Nishi, Yoshio	en_US
dc.date.accessioned	2015-12-02T03:00:54Z	-
dc.date.available	2015-12-02T03:00:54Z	-
dc.date.issued	2014-01-01	en_US
dc.identifier.isbn	978-1-4799-2217-8	en_US
dc.identifier.issn		en_US
dc.identifier.uri	http://hdl.handle.net/11536/128534	-
dc.description.abstract	Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.	en_US
dc.language.iso	en_US	en_US
dc.title	Improved Multi-level Control of RRAM Using Pulse-Train Programming	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF TECHNICAL PROGRAM - 2014 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000358865800034	en_US
dc.citation.woscount	0	en_US
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