標題: A Novel Glitch Reduction Circuitry for Binary-Weighted DAC
作者: Chou, Fang-Ting
Chen, Chia-Min
Chen, Zong-Yi
Hung, Chung-Chih
電機資訊學士班
Undergraduate Honors Program of Electrical Engineering and Computer Science
關鍵字: DAC;Binary-weighted;variable-delay buffer
公開日期: 1-Jan-2014
摘要: This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm(2) core area, and dissipates 19mW from a single 1.8V power supply.
URI: http://hdl.handle.net/11536/128600
ISBN: 978-1-4799-5230-4
ISSN: 
期刊: 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)
起始頁: 240
結束頁: 243
Appears in Collections:Conferences Paper