標題: Reliable crosstalk-driven interconnect optimization
作者: Jiang, IHR
Pan, SR
Chang, YW
Jou, JY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: algorithms;performance;VLSI;interconnect;post-layout optimization;lagrangian relaxation
公開日期: 1-Jan-2006
摘要: As technology advances apace, crosstalk becomes a design metric of comparable importance to area and delay. This article focuses mainly on the crosstalk issue, specifically on the impacts of physical design and process variation on crosstalk. While the feature size shrinks below 0.25 mu m, the impact of process variation on crosstalk increases rapidly. Hence, a crosstalk insensitive design is desirable in the deep submicron regime. In this article, crosstalk sensitivity is referred to as the influence of process variation on crosstalk in a circuit. We show that the lower bound of crosstalk sensitivity grows quadratically, while that of crosstalk increases linearly. Therefore, designers should also consider crosstalk sensitivity, when optimizing other design objectives such as crosstalk, area, and delay. According to our modeling, these objectives are all in posynomial forms, and thus the multiobjective optimization problem can optimally be solved by Lagrangian relaxation. Experimental results show that our method is effective and efficient. For instance, a circuit of 2856 gates and 5272 wires is optimized using 13-minute runtime and 2.8-MB memory on a Pentium III 1.0 GHz PC with 256-MB memory. In particular, by relaxing Lagrange multipliers to the critical paths, it takes only two iterations for all solutions to converge to the global optimal, which is much more efficient than related previous work. This relaxation scheme provides a key insight into the rapid convergence in Lagrangian relaxation.
URI: http://dx.doi.org/10.1016/j.tsf.2005.12.184
http://hdl.handle.net/11536/12874
ISSN: 1084-4309
DOI: 10.1016/j.tsf.2005.12.184
期刊: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
Volume: 11
Issue: 1
起始頁: 88
結束頁: 103
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